d855b261d1
We currently rely on .align directives to ensure that each exception vector entry is the appropriate offset from the vector base address. This is slightly fragile, as were an entry to become too large (greater than 32 A64 instructions), all following entries would be silently shifted until they meet the next alignment boundary. Thus we might execute the wrong code in response to an exception. To prevent this, introduce a new macro, VECTOR_ENTRY, that uses .org directives to position each entry at the precise required offset from the base of a vector. A vector entry which is too large will trigger a build failure rather than a runtime failure which is difficult to debug. For consistency, the base and end of each vector is similarly annotated, with VECTOR_BASE and VECTOR_END, which provide the necessary alignment and symbol exports. The now redundant directives and labels are removed. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18904 6f19259b-4bc3-4df7-8a09-765794883524
81 lines
2.3 KiB
ArmAsm
81 lines
2.3 KiB
ArmAsm
#
|
|
# Copyright (c) 2011-2014, ARM Limited. All rights reserved.
|
|
#
|
|
# This program and the accompanying materials
|
|
# are licensed and made available under the terms and conditions of the BSD License
|
|
# which accompanies this distribution. The full text of the license may be found at
|
|
# http://opensource.org/licenses/bsd-license.php
|
|
#
|
|
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
|
#
|
|
#
|
|
|
|
#include <Chipset/AArch64.h>
|
|
#include <AsmMacroIoLibV8.h>
|
|
#include <Base.h>
|
|
#include <AutoGen.h>
|
|
|
|
.text
|
|
|
|
//============================================================
|
|
//Default Exception Handlers
|
|
//============================================================
|
|
|
|
#define TO_HANDLER \
|
|
EL1_OR_EL2(x1) \
|
|
1: mrs x1, elr_el1 /* EL1 Exception Link Register */ ;\
|
|
b 3f ;\
|
|
2: mrs x1, elr_el2 /* EL2 Exception Link Register */ ;\
|
|
3: bl ASM_PFX(PeiCommonExceptionEntry) ;
|
|
|
|
|
|
//
|
|
// Default Exception handlers: There is no plan to return from any of these exceptions.
|
|
// No context saving at all.
|
|
//
|
|
|
|
VECTOR_BASE(PeiVectorTable)
|
|
|
|
VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_SYNC)
|
|
_DefaultSyncExceptHandler_t:
|
|
mov x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS
|
|
TO_HANDLER
|
|
|
|
VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_IRQ)
|
|
_DefaultIrq_t:
|
|
mov x0, #EXCEPT_AARCH64_IRQ
|
|
TO_HANDLER
|
|
|
|
VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_FIQ)
|
|
_DefaultFiq_t:
|
|
mov x0, #EXCEPT_AARCH64_FIQ
|
|
TO_HANDLER
|
|
|
|
VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_SERR)
|
|
_DefaultSError_t:
|
|
mov x0, #EXCEPT_AARCH64_SERROR
|
|
TO_HANDLER
|
|
|
|
VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_SYNC)
|
|
_DefaultSyncExceptHandler_h:
|
|
mov x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS
|
|
TO_HANDLER
|
|
|
|
VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_IRQ)
|
|
_DefaultIrq_h:
|
|
mov x0, #EXCEPT_AARCH64_IRQ
|
|
TO_HANDLER
|
|
|
|
VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_FIQ)
|
|
_DefaultFiq_h:
|
|
mov x0, #EXCEPT_AARCH64_FIQ
|
|
TO_HANDLER
|
|
|
|
VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_SERR)
|
|
_DefaultSError_h:
|
|
mov x0, #EXCEPT_AARCH64_SERROR
|
|
TO_HANDLER
|
|
|
|
VECTOR_END(PeiVectorTable)
|