dba79765c4
Memory layout in CLoud Hypervisor for arm is changed and is different with Qemu, thus we should build its own PeiMemInfoLib. The main change in the memory layout is that normal ram may not contiguous under 4G. The top 64M under 4G is reserved for 32bit device. What this patch does: 1. get all of the memory node from DT; 2. Init page table for each memory node; 3. Add all of the memory nodes to Hob; Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Jianyong Wu <jianyong.wu@arm.com>
43 lines
1.2 KiB
C
43 lines
1.2 KiB
C
/** @file
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Copyright (c) 2022, Arm Limited. All rights reserved.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef CLOUDHV_VIRT_MEM_INFO_LIB_H_
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#define CLOUDHV_VIRT_MEM_INFO_LIB_H_
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//
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// Cloud Hypervisor may have more than one memory nodes. Even there is no limit for that,
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// I think 10 is enough in general.
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//
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#define CLOUDHV_MAX_MEM_NODE_NUM 10
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// Record memory node info (base address and size)
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typedef struct {
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UINT64 Base;
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UINT64 Size;
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} CLOUDHV_MEM_NODE_INFO;
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// Number of Virtual Memory Map Descriptors
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#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS (4 + CLOUDHV_MAX_MEM_NODE_NUM)
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//
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// Core peripherals such as the UART, the GIC and the RTC are
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// all mapped in the 'miscellaneous device I/O' region, which we just map
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// in its entirety rather than device by device. Note that it does not
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// cover any of the NOR flash banks or PCI resource windows.
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//
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#define MACH_VIRT_PERIPH_BASE 0x00400000
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#define MACH_VIRT_PERIPH_SIZE 0x0FC00000
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//
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// The top of the 64M memory region under 4GB reserved for device
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//
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#define TOP_32BIT_DEVICE_BASE 0xFC000000
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#define TOP_32BIT_DEVICE_SIZE 0x04000000
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#endif // CLOUDHV_VIRT_MEM_INFO_LIB_H_
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