decaac5d0d
ARM uses the low order bit of a branch target address to decide in which execution mode (ARM or Thumb) a function needs to be called. In order for this to work across object files, ELF function symbols will have the low bit set if they were emitted in Thumb mode and cleared otherwise. This annotation is only emitted if the ELF symbols are annotated as function, since taking the address of some data symbol (e.g., a literal) should not produce a value with the low bit set, even if it appears in an object file containing Thumb code. This means that all functions coded in assembler must have this function annotation, or they may end up getting called in the wrong mode, crashing the program. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Liming Gao <liming.gao@intel.com>
95 lines
3.2 KiB
ArmAsm
95 lines
3.2 KiB
ArmAsm
#------------------------------------------------------------------------------
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#
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# Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
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#
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# This program and the accompanying materials are licensed and made available
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# under the terms and conditions of the BSD License which accompanies this
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# distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#------------------------------------------------------------------------------
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.text
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.thumb
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.syntax unified
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.align 5
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.type ASM_PFX(InternalMemSetMem16), %function
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ASM_GLOBAL ASM_PFX(InternalMemSetMem16)
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ASM_PFX(InternalMemSetMem16):
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uxth r2, r2
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lsl r1, r1, #1
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orr r2, r2, r2, lsl #16
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b 0f
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.type ASM_PFX(InternalMemSetMem32), %function
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ASM_GLOBAL ASM_PFX(InternalMemSetMem32)
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ASM_PFX(InternalMemSetMem32):
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lsl r1, r1, #2
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b 0f
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.type ASM_PFX(InternalMemSetMem64), %function
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ASM_GLOBAL ASM_PFX(InternalMemSetMem64)
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ASM_PFX(InternalMemSetMem64):
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lsl r1, r1, #3
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b 1f
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.align 5
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.type ASM_PFX(InternalMemSetMem), %function
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ASM_GLOBAL ASM_PFX(InternalMemSetMem)
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ASM_PFX(InternalMemSetMem):
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uxtb r2, r2
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orr r2, r2, r2, lsl #8
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orr r2, r2, r2, lsl #16
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b 0f
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.type ASM_PFX(InternalMemZeroMem), %function
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ASM_GLOBAL ASM_PFX(InternalMemZeroMem)
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ASM_PFX(InternalMemZeroMem):
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movs r2, #0
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0: mov r3, r2
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1: push {r4, lr}
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cmp r1, #16 // fewer than 16 bytes of input?
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add r1, r1, r0 // r1 := dst + length
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add lr, r0, #16
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blt 2f
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bic lr, lr, #15 // align output pointer
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str r2, [r0] // potentially unaligned store of 4 bytes
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str r3, [r0, #4] // potentially unaligned store of 4 bytes
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str r2, [r0, #8] // potentially unaligned store of 4 bytes
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str r3, [r0, #12] // potentially unaligned store of 4 bytes
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beq 1f
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0: add lr, lr, #16 // advance the output pointer by 16 bytes
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subs r4, r1, lr // past the output?
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blt 3f // break out of the loop
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strd r2, r3, [lr, #-16] // aligned store of 16 bytes
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strd r2, r3, [lr, #-8]
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bne 0b // goto beginning of loop
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1: pop {r4, pc}
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2: subs r4, r1, lr
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3: adds r4, r4, #16
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subs r1, r1, #8
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cmp r4, #4 // between 4 and 15 bytes?
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blt 4f
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cmp r4, #8 // between 8 and 15 bytes?
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sub r4, lr, #16
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str r2, [r4] // overlapping store of 4 + (4 + 4) + 4 bytes
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it gt
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strgt.n r3, [r4, #4]
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it gt
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strgt.n r2, [r1]
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str r3, [r1, #4]
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pop {r4, pc}
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4: cmp r4, #2 // 2 or 3 bytes?
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strb r2, [lr, #-16] // store 1 byte
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it ge
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strhge.n r2, [r1, #6] // store 2 bytes
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pop {r4, pc}
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