e2289d19d8
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275 Move all the SEV specific function in AmdSev.c. No functional change intended. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Michael Roth <michael.roth@amd.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Suggested-by: Jiewen Yao <Jiewen.yao@intel.com> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
120 lines
3.4 KiB
NASM
120 lines
3.4 KiB
NASM
;------------------------------------------------------------------------------ ;
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; Copyright (c) 2021, AMD Inc. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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; Module Name:
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;
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; AmdSev.nasm
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;
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; Abstract:
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;
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; This provides helper used by the MpFunc.nasm. If AMD SEV-ES is active
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; then helpers perform the additional setups (such as GHCB).
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;
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;-------------------------------------------------------------------------------
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%define SIZE_4KB 0x1000
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;
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; The function checks whether SEV-ES is enabled, if enabled
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; then setup the GHCB page.
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;
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SevEsSetupGhcb:
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lea edi, [esi + MP_CPU_EXCHANGE_INFO_FIELD (SevEsIsEnabled)]
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cmp byte [edi], 1 ; SevEsIsEnabled
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jne SevEsSetupGhcbExit
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;
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; program GHCB
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; Each page after the GHCB is a per-CPU page, so the calculation programs
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; a GHCB to be every 8KB.
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;
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mov eax, SIZE_4KB
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shl eax, 1 ; EAX = SIZE_4K * 2
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mov ecx, ebx
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mul ecx ; EAX = SIZE_4K * 2 * CpuNumber
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mov edi, esi
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add edi, MP_CPU_EXCHANGE_INFO_FIELD (GhcbBase)
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add rax, qword [edi]
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mov rdx, rax
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shr rdx, 32
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mov rcx, 0xc0010130
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wrmsr
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SevEsSetupGhcbExit:
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OneTimeCallRet SevEsSetupGhcb
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;
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; The function checks whether SEV-ES is enabled, if enabled, use
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; the GHCB
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;
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SevEsGetApicId:
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lea edi, [esi + MP_CPU_EXCHANGE_INFO_FIELD (SevEsIsEnabled)]
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cmp byte [edi], 1 ; SevEsIsEnabled
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jne SevEsGetApicIdExit
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;
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; Since we don't have a stack yet, we can't take a #VC
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; exception. Use the GHCB protocol to perform the CPUID
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; calls.
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;
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mov rcx, 0xc0010130
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rdmsr
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shl rdx, 32
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or rax, rdx
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mov rdi, rax ; RDI now holds the original GHCB GPA
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mov rdx, 0 ; CPUID function 0
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mov rax, 0 ; RAX register requested
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or rax, 4
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wrmsr
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rep vmmcall
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rdmsr
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cmp edx, 0bh
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jb NoX2ApicSevEs ; CPUID level below CPUID_EXTENDED_TOPOLOGY
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mov rdx, 0bh ; CPUID function 0x0b
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mov rax, 040000000h ; RBX register requested
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or rax, 4
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wrmsr
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rep vmmcall
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rdmsr
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test edx, 0ffffh
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jz NoX2ApicSevEs ; CPUID.0BH:EBX[15:0] is zero
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mov rdx, 0bh ; CPUID function 0x0b
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mov rax, 0c0000000h ; RDX register requested
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or rax, 4
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wrmsr
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rep vmmcall
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rdmsr
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; Processor is x2APIC capable; 32-bit x2APIC ID is now in EDX
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jmp RestoreGhcb
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NoX2ApicSevEs:
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; Processor is not x2APIC capable, so get 8-bit APIC ID
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mov rdx, 1 ; CPUID function 1
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mov rax, 040000000h ; RBX register requested
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or rax, 4
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wrmsr
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rep vmmcall
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rdmsr
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shr edx, 24
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RestoreGhcb:
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mov rbx, rdx ; Save x2APIC/APIC ID
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mov rdx, rdi ; RDI holds the saved GHCB GPA
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shr rdx, 32
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mov eax, edi
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wrmsr
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mov rdx, rbx
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; x2APIC ID or APIC ID is in EDX
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jmp GetProcessorNumber
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SevEsGetApicIdExit:
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OneTimeCallRet SevEsGetApicId
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