RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429 There are below changes in PlatformInitLib for Tdx guest: 1. Publish ram regions In Tdx guest, the system memory is passed in TdHob by host VMM. So the major task of PlatformTdxPublishRamRegions is to walk thru the TdHob list and transfer the ResourceDescriptorHob and MemoryAllocationHob to the hobs in DXE phase. 2. Build MemoryAllocationHob for Tdx Mailbox and Ovmf work area. 3. Update of PlatformAddressWidthInitialization. The physical address width that Tdx guest supports is either 48 or 52. 4. Update of PlatformMemMapInitialization. 0xA0000 - 0xFFFFF is VGA bios region. Platform initialization marks the region as MMIO region. Dxe code maps MMIO region as IO region. As TDX guest, MMIO region is maps as shared. However VGA BIOS doesn't need to be shared. Guest TDX Linux maps VGA BIOS as private and accesses for BIOS and stuck on repeating EPT violation. VGA BIOS (more generally ROM region) should be private. Skip marking VGA BIOA region [0xa000, 0xfffff] as MMIO in HOB. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Min Xu <min.m.xu@intel.com>
238 lines
5.3 KiB
C
238 lines
5.3 KiB
C
/** @file
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PlatformInitLib header file.
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef PLATFORM_INIT_LIB_H_
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#define PLATFORM_INIT_LIB_H_
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#include <PiPei.h>
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#pragma pack(1)
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typedef struct {
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EFI_HOB_GUID_TYPE GuidHeader;
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UINT16 HostBridgeDevId;
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UINT64 PcdConfidentialComputingGuestAttr;
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BOOLEAN SevEsIsEnabled;
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UINT32 BootMode;
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BOOLEAN S3Supported;
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BOOLEAN SmmSmramRequire;
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BOOLEAN Q35SmramAtDefaultSmbase;
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UINT16 Q35TsegMbytes;
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UINT64 FirstNonAddress;
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UINT8 PhysMemAddressWidth;
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UINT32 Uc32Base;
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UINT32 Uc32Size;
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BOOLEAN PcdSetNxForStack;
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UINT64 PcdTdxSharedBitMask;
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UINT64 PcdPciMmio64Base;
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UINT64 PcdPciMmio64Size;
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UINT32 PcdPciMmio32Base;
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UINT32 PcdPciMmio32Size;
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UINT64 PcdPciIoBase;
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UINT64 PcdPciIoSize;
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UINT64 PcdEmuVariableNvStoreReserved;
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UINT32 PcdCpuBootLogicalProcessorNumber;
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UINT32 PcdCpuMaxLogicalProcessorNumber;
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UINT32 DefaultMaxCpuNumber;
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UINT32 S3AcpiReservedMemoryBase;
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UINT32 S3AcpiReservedMemorySize;
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} EFI_HOB_PLATFORM_INFO;
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#pragma pack()
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/**
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Reads 8-bits of CMOS data.
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Reads the 8-bits of CMOS data at the location specified by Index.
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The 8-bit read value is returned.
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@param Index The CMOS location to read.
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@return The value read.
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**/
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UINT8
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EFIAPI
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PlatformCmosRead8 (
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IN UINTN Index
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);
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/**
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Writes 8-bits of CMOS data.
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Writes 8-bits of CMOS data to the location specified by Index
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with the value specified by Value and returns Value.
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@param Index The CMOS location to write.
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@param Value The value to write to CMOS.
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@return The value written to CMOS.
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**/
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UINT8
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EFIAPI
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PlatformCmosWrite8 (
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IN UINTN Index,
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IN UINT8 Value
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);
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/**
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Dump the CMOS content
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*/
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VOID
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EFIAPI
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PlatformDebugDumpCmos (
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VOID
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);
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VOID
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EFIAPI
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PlatformAddIoMemoryBaseSizeHob (
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IN EFI_PHYSICAL_ADDRESS MemoryBase,
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IN UINT64 MemorySize
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);
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VOID
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EFIAPI
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PlatformAddIoMemoryRangeHob (
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IN EFI_PHYSICAL_ADDRESS MemoryBase,
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IN EFI_PHYSICAL_ADDRESS MemoryLimit
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);
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VOID
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EFIAPI
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PlatformAddMemoryBaseSizeHob (
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IN EFI_PHYSICAL_ADDRESS MemoryBase,
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IN UINT64 MemorySize
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);
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VOID
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EFIAPI
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PlatformAddMemoryRangeHob (
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IN EFI_PHYSICAL_ADDRESS MemoryBase,
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IN EFI_PHYSICAL_ADDRESS MemoryLimit
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);
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VOID
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EFIAPI
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PlatformAddReservedMemoryBaseSizeHob (
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IN EFI_PHYSICAL_ADDRESS MemoryBase,
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IN UINT64 MemorySize,
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IN BOOLEAN Cacheable
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);
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VOID
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EFIAPI
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PlatformQemuUc32BaseInitialization (
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IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob
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);
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UINT32
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EFIAPI
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PlatformGetSystemMemorySizeBelow4gb (
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IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob
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);
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/**
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Initialize the PhysMemAddressWidth field in PlatformInfoHob based on guest RAM size.
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**/
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VOID
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EFIAPI
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PlatformAddressWidthInitialization (
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IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob
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);
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/**
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Peform Memory Detection for QEMU / KVM
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**/
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VOID
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EFIAPI
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PlatformQemuInitializeRam (
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IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob
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);
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VOID
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EFIAPI
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PlatformQemuInitializeRamForS3 (
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IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob
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);
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VOID
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EFIAPI
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PlatformMemMapInitialization (
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IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob
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);
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/**
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* Fetch "opt/ovmf/PcdSetNxForStack" from QEMU
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*
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* @param Setting The pointer to the setting of "/opt/ovmf/PcdSetNxForStack".
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* @return EFI_SUCCESS Successfully fetch the settings.
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*/
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EFI_STATUS
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EFIAPI
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PlatformNoexecDxeInitialization (
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IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob
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);
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VOID
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EFIAPI
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PlatformMiscInitialization (
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IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob
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);
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/**
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Fetch the boot CPU count and the possible CPU count from QEMU, and expose
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them to UefiCpuPkg modules.
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**/
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VOID
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EFIAPI
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PlatformMaxCpuCountInitialization (
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IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob
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);
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/**
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In Tdx guest, some information need to be passed from host VMM to guest
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firmware. For example, the memory resource, etc. These information are
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prepared by host VMM and put in HobList which is described in TdxMetadata.
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Information in HobList is treated as external input. From the security
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perspective before it is consumed, it should be validated.
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@retval EFI_SUCCESS Successfully process the hoblist
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@retval Others Other error as indicated
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**/
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EFI_STATUS
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EFIAPI
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ProcessTdxHobList (
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VOID
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);
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/**
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In Tdx guest, the system memory is passed in TdHob by host VMM. So
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the major task of PlatformTdxPublishRamRegions is to walk thru the
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TdHob list and transfer the ResourceDescriptorHob and MemoryAllocationHob
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to the hobs in DXE phase.
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MemoryAllocationHob should also be created for Mailbox and Ovmf work area.
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**/
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VOID
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EFIAPI
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PlatformTdxPublishRamRegions (
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VOID
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);
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#endif // PLATFORM_INIT_LIB_H_
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