e51a677dea
For historical reasons, the files under ArmLib are split up into 'common' files under Common/, containing common C files as well as AArch64 and Arm specific asm files, and ArmV7 and AArch64 files under ArmV7/ and AArch64/, respectively. This presumably dates back to the time when ArmLib supported different revisions of the 32-bit architecture (i.e., pre-V7) Since the PI spec requires V7 or later, we can simplify this to Arm/ and AArch64, which aligns ArmLib with the majority of other modules that carry ARM or AArch64 specific code. So move the files around so that shared files live at the same level as ArmBaseLib.inf, and ARM/AArch64 specific files live in Arm/ or AArch64/, respectively. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
170 lines
4.2 KiB
NASM
170 lines
4.2 KiB
NASM
//------------------------------------------------------------------------------
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//
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// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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// Copyright (c) 2011 - 2016, ARM Limited. All rights reserved.
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//
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// This program and the accompanying materials
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// are licensed and made available under the terms and conditions of the BSD License
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// which accompanies this distribution. The full text of the license may be found at
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// http://opensource.org/licenses/bsd-license.php
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//
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// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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//
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//------------------------------------------------------------------------------
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INCLUDE AsmMacroIoLib.inc
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INCLUDE AsmMacroExport.inc
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RVCT_ASM_EXPORT ArmReadMidr
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mrc p15,0,R0,c0,c0,0
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bx LR
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RVCT_ASM_EXPORT ArmCacheInfo
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mrc p15,0,R0,c0,c0,1
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bx LR
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RVCT_ASM_EXPORT ArmGetInterruptState
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mrs R0,CPSR
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tst R0,#0x80 // Check if IRQ is enabled.
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moveq R0,#1
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movne R0,#0
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bx LR
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RVCT_ASM_EXPORT ArmGetFiqState
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mrs R0,CPSR
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tst R0,#0x40 // Check if FIQ is enabled.
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moveq R0,#1
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movne R0,#0
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bx LR
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RVCT_ASM_EXPORT ArmSetDomainAccessControl
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mcr p15,0,r0,c3,c0,0
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bx lr
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RVCT_ASM_EXPORT CPSRMaskInsert
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stmfd sp!, {r4-r12, lr} // save all the banked registers
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mov r3, sp // copy the stack pointer into a non-banked register
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mrs r2, cpsr // read the cpsr
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bic r2, r2, r0 // clear mask in the cpsr
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and r1, r1, r0 // clear bits outside the mask in the input
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orr r2, r2, r1 // set field
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msr cpsr_cxsf, r2 // write back cpsr (may have caused a mode switch)
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isb
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mov sp, r3 // restore stack pointer
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ldmfd sp!, {r4-r12, lr} // restore registers
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bx lr // return (hopefully thumb-safe!) // return (hopefully thumb-safe!)
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RVCT_ASM_EXPORT CPSRRead
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mrs r0, cpsr
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bx lr
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RVCT_ASM_EXPORT ArmReadCpacr
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mrc p15, 0, r0, c1, c0, 2
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bx lr
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RVCT_ASM_EXPORT ArmWriteCpacr
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mcr p15, 0, r0, c1, c0, 2
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isb
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bx lr
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RVCT_ASM_EXPORT ArmWriteAuxCr
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mcr p15, 0, r0, c1, c0, 1
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bx lr
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RVCT_ASM_EXPORT ArmReadAuxCr
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mrc p15, 0, r0, c1, c0, 1
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bx lr
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RVCT_ASM_EXPORT ArmSetTTBR0
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mcr p15,0,r0,c2,c0,0
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isb
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bx lr
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RVCT_ASM_EXPORT ArmSetTTBCR
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mcr p15, 0, r0, c2, c0, 2
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isb
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bx lr
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RVCT_ASM_EXPORT ArmGetTTBR0BaseAddress
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mrc p15,0,r0,c2,c0,0
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MOV32 r1, 0xFFFFC000
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and r0, r0, r1
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isb
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bx lr
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//
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//VOID
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//ArmUpdateTranslationTableEntry (
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// IN VOID *TranslationTableEntry // R0
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// IN VOID *MVA // R1
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// );
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RVCT_ASM_EXPORT ArmUpdateTranslationTableEntry
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mcr p15,0,R0,c7,c14,1 // DCCIMVAC Clean data cache by MVA
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dsb
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mcr p15,0,R1,c8,c7,1 // TLBIMVA TLB Invalidate MVA
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mcr p15,0,R9,c7,c5,6 // BPIALL Invalidate Branch predictor array. R9 == NoOp
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dsb
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isb
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bx lr
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RVCT_ASM_EXPORT ArmInvalidateTlb
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mov r0,#0
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mcr p15,0,r0,c8,c7,0
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mcr p15,0,R9,c7,c5,6 // BPIALL Invalidate Branch predictor array. R9 == NoOp
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dsb
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isb
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bx lr
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RVCT_ASM_EXPORT ArmReadScr
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mrc p15, 0, r0, c1, c1, 0
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bx lr
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RVCT_ASM_EXPORT ArmWriteScr
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mcr p15, 0, r0, c1, c1, 0
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isb
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bx lr
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RVCT_ASM_EXPORT ArmReadHVBar
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mrc p15, 4, r0, c12, c0, 0
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bx lr
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RVCT_ASM_EXPORT ArmWriteHVBar
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mcr p15, 4, r0, c12, c0, 0
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bx lr
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RVCT_ASM_EXPORT ArmReadMVBar
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mrc p15, 0, r0, c12, c0, 1
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bx lr
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RVCT_ASM_EXPORT ArmWriteMVBar
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mcr p15, 0, r0, c12, c0, 1
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bx lr
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RVCT_ASM_EXPORT ArmCallWFE
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wfe
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bx lr
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RVCT_ASM_EXPORT ArmCallSEV
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sev
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bx lr
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RVCT_ASM_EXPORT ArmReadSctlr
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mrc p15, 0, r0, c1, c0, 0 // Read SCTLR into R0 (Read control register configuration data)
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bx lr
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RVCT_ASM_EXPORT ArmReadCpuActlr
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mrc p15, 0, r0, c1, c0, 1
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bx lr
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RVCT_ASM_EXPORT ArmWriteCpuActlr
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mcr p15, 0, r0, c1, c0, 1
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dsb
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isb
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bx lr
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END
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