9d510e61fc
https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
131 lines
3.1 KiB
NASM
131 lines
3.1 KiB
NASM
;; @file
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; This is the assembly code for transferring to control to OS S3 waking vector
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; for X64 platform
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;
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; Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
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;
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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;;
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extern ASM_PFX(mOriginalHandler)
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extern ASM_PFX(PageFaultHandler)
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DEFAULT REL
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SECTION .text
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global ASM_PFX(AsmFixAddress16)
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global ASM_PFX(AsmJmpAddr32)
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global ASM_PFX(AsmTransferControl)
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ASM_PFX(AsmTransferControl):
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; rcx S3WakingVector :DWORD
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; rdx AcpiLowMemoryBase :DWORD
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lea eax, [.0]
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mov r8, 0x2800000000
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or rax, r8
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push rax
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shrd ebx, ecx, 20
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and ecx, 0xf
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mov bx, cx
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mov [@jmp_addr + 1], ebx
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retf
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BITS 16
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.0:
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mov ax, 0x30
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mov ds, ax
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mov es, ax
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mov fs, ax
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mov gs, ax
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mov ss, ax
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mov eax, cr0
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mov ebx, cr4
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and eax, ((~ 0x80000001) & 0xffffffff)
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and bl, ~ (1 << 5)
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mov cr0, eax
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mov ecx, 0xc0000080
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rdmsr
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and ah, ~ 1
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wrmsr
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mov cr4, ebx
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@jmp_addr:
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jmp 0x0:0x0
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global ASM_PFX(AsmTransferControl32)
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ASM_PFX(AsmTransferControl32):
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BITS 32
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; S3WakingVector :DWORD
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; AcpiLowMemoryBase :DWORD
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push ebp
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mov ebp, esp
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DB 0x8d, 0x5 ; lea eax, AsmTransferControl16
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ASM_PFX(AsmFixAddress16): DD 0
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push 0x28 ; CS
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push eax
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retf
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global ASM_PFX(AsmTransferControl16)
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ASM_PFX(AsmTransferControl16):
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BITS 16
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mov ax, 0x30
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o32 mov ds, eax
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o32 mov es, eax
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o32 mov fs, eax
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o32 mov gs, eax
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o32 mov ss, eax
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mov eax, cr0 ; Get control register 0
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and eax, 0fffffffeh ; Clear PE bit (bit #0)
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mov cr0, eax ; Activate real mode
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DB 0xea ; jmp far AsmJmpAddr32
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ASM_PFX(AsmJmpAddr32): DD 0
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global ASM_PFX(PageFaultHandlerHook)
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ASM_PFX(PageFaultHandlerHook):
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BITS 64
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push rax ; save all volatile registers
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push rcx
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push rdx
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push r8
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push r9
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push r10
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push r11
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; save volatile fp registers
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add rsp, -0x68
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stmxcsr [rsp + 0x60]
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movdqa [rsp + 0x0], xmm0
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movdqa [rsp + 0x10], xmm1
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movdqa [rsp + 0x20], xmm2
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movdqa [rsp + 0x30], xmm3
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movdqa [rsp + 0x40], xmm4
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movdqa [rsp + 0x50], xmm5
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add rsp, -0x20
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call ASM_PFX(PageFaultHandler)
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add rsp, 0x20
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; load volatile fp registers
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ldmxcsr [rsp + 0x60]
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movdqa xmm0, [rsp + 0x0]
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movdqa xmm1, [rsp + 0x10]
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movdqa xmm2, [rsp + 0x20]
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movdqa xmm3, [rsp + 0x30]
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movdqa xmm4, [rsp + 0x40]
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movdqa xmm5, [rsp + 0x50]
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add rsp, 0x68
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test al, al
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pop r11
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pop r10
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pop r9
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pop r8
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pop rdx
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pop rcx
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pop rax ; restore all volatile registers
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jnz .1
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jmp qword [ASM_PFX(mOriginalHandler)]
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.1:
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add rsp, 0x8 ; skip error code for PF
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iretq
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