git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@5257 6f19259b-4bc3-4df7-8a09-765794883524
		
			
				
	
	
		
			162 lines
		
	
	
		
			5.1 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			162 lines
		
	
	
		
			5.1 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
/** @file
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  x64 Long Mode Virtual Memory Management Definitions  
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  References:
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    1) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 1:Basic Architecture, Intel
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    2) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel
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    3) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel
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    4) AMD64 Architecture Programmer's Manual Volume 2: System Programming
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Copyright (c) 2006 - 2008, Intel Corporation. <BR>
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All rights reserved. This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution.  The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/  
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#ifndef _VIRTUAL_MEMORY_H_
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#define _VIRTUAL_MEMORY_H_
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#define SYS_CODE64_SEL 0x38
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#pragma pack(1)
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typedef union {
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  struct {
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    UINT32  LimitLow    : 16;
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    UINT32  BaseLow     : 16;
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    UINT32  BaseMid     : 8;
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    UINT32  Type        : 4;
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    UINT32  System      : 1;
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    UINT32  Dpl         : 2;
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    UINT32  Present     : 1;
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    UINT32  LimitHigh   : 4;
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    UINT32  Software    : 1;
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    UINT32  Reserved    : 1;
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    UINT32  DefaultSize : 1;
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    UINT32  Granularity : 1;
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    UINT32  BaseHigh    : 8;
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  } Bits;
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  UINT64  Uint64;
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} IA32_GDT;
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typedef struct {
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  IA32_IDT_GATE_DESCRIPTOR  Ia32IdtEntry;
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  UINT32                    Offset32To63;
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  UINT32                    Reserved;
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} X64_IDT_GATE_DESCRIPTOR;
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//
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// Page-Map Level-4 Offset (PML4) and
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// Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB
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//
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typedef union {
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  struct {
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    UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory
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    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write
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    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User
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    UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching
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    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached
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    UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)
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    UINT64  Reserved:1;               // Reserved
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    UINT64  MustBeZero:2;             // Must Be Zero
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    UINT64  Available:3;              // Available for use by system software
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    UINT64  PageTableBaseAddress:40;  // Page Table Base Address
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    UINT64  AvabilableHigh:11;        // Available for use by system software
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    UINT64  Nx:1;                     // No Execute bit
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  } Bits;
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  UINT64    Uint64;
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} PAGE_MAP_AND_DIRECTORY_POINTER;
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//
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// Page Table Entry 2MB
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//
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typedef union {
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  struct {
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    UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory
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    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write
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    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User
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    UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching
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    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached
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    UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)
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    UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page
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    UINT64  MustBe1:1;                // Must be 1 
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    UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
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    UINT64  Available:3;              // Available for use by system software
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    UINT64  PAT:1;                    //
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    UINT64  MustBeZero:8;             // Must be zero;
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    UINT64  PageTableBaseAddress:31;  // Page Table Base Address
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    UINT64  AvabilableHigh:11;        // Available for use by system software
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    UINT64  Nx:1;                     // 0 = Execute Code, 1 = No Code Execution
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  } Bits;
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  UINT64    Uint64;
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} PAGE_TABLE_ENTRY;
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#pragma pack()
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/**
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  Allocates and fills in the Page Directory and Page Table Entries to
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  establish a 1:1 Virtual to Physical mapping.
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  @param  NumberOfProcessorPhysicalAddressBits  Number of processor address bits 
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                                                to use. Limits the number of page 
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                                                table entries  to the physical 
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                                                address space. 
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  @return EFI_SUCCESS           The 1:1 Virtual to Physical identity mapping was created
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**/
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UINTN
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CreateIdentityMappingPageTables (
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  VOID
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  );
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/**
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  Fix up the vector number in the vector code.
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  @param VectorBase   Base address of the vector handler.
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  @param VectorNum    Index of vector.
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**/
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VOID
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EFIAPI
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AsmVectorFixup (
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  VOID    *VectorBase,
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  UINT8   VectorNum
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  );
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/**
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  Get the information of vector template.
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  @param TemplateBase   Base address of the template code.
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  @return               Size of the Template code.
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**/
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UINTN
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EFIAPI
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AsmGetVectorTemplatInfo (
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  OUT   VOID  **TemplateBase
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  );
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#endif 
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