4059386c70
https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
114 lines
2.9 KiB
ArmAsm
114 lines
2.9 KiB
ArmAsm
#------------------------------------------------------------------------------
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#
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# Copyright (c) 2011 - 2013, ARM Limited. All rights reserved.
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# Copyright (c) 2016, Linaro Limited. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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#------------------------------------------------------------------------------
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#include <AsmMacroIoLibV8.h>
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ASM_FUNC(ArmReadCntFrq)
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mrs x0, cntfrq_el0 // Read CNTFRQ
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ret
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# NOTE - Can only write while at highest implemented EL level (EL3 on model). Else ReadOnly (EL2, EL1, EL0)
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ASM_FUNC(ArmWriteCntFrq)
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msr cntfrq_el0, x0 // Write to CNTFRQ
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ret
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ASM_FUNC(ArmReadCntPct)
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mrs x0, cntpct_el0 // Read CNTPCT (Physical counter register)
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ret
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ASM_FUNC(ArmReadCntkCtl)
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mrs x0, cntkctl_el1 // Read CNTK_CTL (Timer PL1 Control Register)
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ret
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ASM_FUNC(ArmWriteCntkCtl)
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msr cntkctl_el1, x0 // Write to CNTK_CTL (Timer PL1 Control Register)
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ret
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ASM_FUNC(ArmReadCntpTval)
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mrs x0, cntp_tval_el0 // Read CNTP_TVAL (PL1 physical timer value register)
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ret
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ASM_FUNC(ArmWriteCntpTval)
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msr cntp_tval_el0, x0 // Write to CNTP_TVAL (PL1 physical timer value register)
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ret
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ASM_FUNC(ArmReadCntpCtl)
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mrs x0, cntp_ctl_el0 // Read CNTP_CTL (PL1 Physical Timer Control Register)
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ret
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ASM_FUNC(ArmWriteCntpCtl)
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msr cntp_ctl_el0, x0 // Write to CNTP_CTL (PL1 Physical Timer Control Register)
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ret
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ASM_FUNC(ArmReadCntvTval)
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mrs x0, cntv_tval_el0 // Read CNTV_TVAL (Virtual Timer Value register)
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ret
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ASM_FUNC(ArmWriteCntvTval)
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msr cntv_tval_el0, x0 // Write to CNTV_TVAL (Virtual Timer Value register)
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ret
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ASM_FUNC(ArmReadCntvCtl)
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mrs x0, cntv_ctl_el0 // Read CNTV_CTL (Virtual Timer Control Register)
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ret
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ASM_FUNC(ArmWriteCntvCtl)
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msr cntv_ctl_el0, x0 // Write to CNTV_CTL (Virtual Timer Control Register)
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ret
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ASM_FUNC(ArmReadCntvCt)
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mrs x0, cntvct_el0 // Read CNTVCT (Virtual Count Register)
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ret
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ASM_FUNC(ArmReadCntpCval)
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mrs x0, cntp_cval_el0 // Read CNTP_CTVAL (Physical Timer Compare Value Register)
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ret
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ASM_FUNC(ArmWriteCntpCval)
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msr cntp_cval_el0, x0 // Write to CNTP_CTVAL (Physical Timer Compare Value Register)
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ret
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ASM_FUNC(ArmReadCntvCval)
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mrs x0, cntv_cval_el0 // Read CNTV_CTVAL (Virtual Timer Compare Value Register)
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ret
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ASM_FUNC(ArmWriteCntvCval)
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msr cntv_cval_el0, x0 // write to CNTV_CTVAL (Virtual Timer Compare Value Register)
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ret
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ASM_FUNC(ArmReadCntvOff)
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mrs x0, cntvoff_el2 // Read CNTVOFF (virtual Offset register)
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ret
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ASM_FUNC(ArmWriteCntvOff)
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msr cntvoff_el2, x0 // Write to CNTVOFF (Virtual Offset register)
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ret
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ASM_FUNCTION_REMOVE_IF_UNREFERENCED
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