cc15a619a6
This patch fixes the following Ecc reported error: The #ifndef at the start of an include file should have one postfix underscore, and no prefix underscore character Some include guards have been modified to match the name of the header file. Some comments have also been added on the closing '#endif'. Cc: Bret Barkelew <bret.barkelew@microsoft.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
190 lines
6.7 KiB
C
190 lines
6.7 KiB
C
/** @file
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ArmLibPrivate.h
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Copyright (c) 2020, NUVIA Inc. All rights reserved.<BR>
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Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef ARM_LIB_PRIVATE_H_
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#define ARM_LIB_PRIVATE_H_
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#define CACHE_SIZE_4_KB (3UL)
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#define CACHE_SIZE_8_KB (4UL)
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#define CACHE_SIZE_16_KB (5UL)
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#define CACHE_SIZE_32_KB (6UL)
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#define CACHE_SIZE_64_KB (7UL)
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#define CACHE_SIZE_128_KB (8UL)
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#define CACHE_ASSOCIATIVITY_DIRECT (0UL)
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#define CACHE_ASSOCIATIVITY_4_WAY (2UL)
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#define CACHE_ASSOCIATIVITY_8_WAY (3UL)
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#define CACHE_PRESENT (0UL)
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#define CACHE_NOT_PRESENT (1UL)
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#define CACHE_LINE_LENGTH_32_BYTES (2UL)
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#define SIZE_FIELD_TO_CACHE_SIZE(x) (((x) >> 6) & 0x0F)
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#define SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(x) (((x) >> 3) & 0x07)
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#define SIZE_FIELD_TO_CACHE_PRESENCE(x) (((x) >> 2) & 0x01)
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#define SIZE_FIELD_TO_CACHE_LINE_LENGTH(x) (((x) >> 0) & 0x03)
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#define DATA_CACHE_SIZE_FIELD(x) (((x) >> 12) & 0x0FFF)
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#define INSTRUCTION_CACHE_SIZE_FIELD(x) (((x) >> 0) & 0x0FFF)
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#define DATA_CACHE_SIZE(x) (SIZE_FIELD_TO_CACHE_SIZE(DATA_CACHE_SIZE_FIELD(x)))
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#define DATA_CACHE_ASSOCIATIVITY(x) (SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(DATA_CACHE_SIZE_FIELD(x)))
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#define DATA_CACHE_PRESENT(x) (SIZE_FIELD_TO_CACHE_PRESENCE(DATA_CACHE_SIZE_FIELD(x)))
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#define DATA_CACHE_LINE_LENGTH(x) (SIZE_FIELD_TO_CACHE_LINE_LENGTH(DATA_CACHE_SIZE_FIELD(x)))
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#define INSTRUCTION_CACHE_SIZE(x) (SIZE_FIELD_TO_CACHE_SIZE(INSTRUCTION_CACHE_SIZE_FIELD(x)))
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#define INSTRUCTION_CACHE_ASSOCIATIVITY(x) (SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(INSTRUCTION_CACHE_SIZE_FIELD(x)))
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#define INSTRUCTION_CACHE_PRESENT(x) (SIZE_FIELD_TO_CACHE_PRESENCE(INSTRUCTION_CACHE_SIZE_FIELD(x)))
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#define INSTRUCTION_CACHE_LINE_LENGTH(x) (SIZE_FIELD_TO_CACHE_LINE_LENGTH(INSTRUCTION_CACHE_SIZE_FIELD(x)))
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#define CACHE_TYPE(x) (((x) >> 25) & 0x0F)
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#define CACHE_TYPE_WRITE_BACK (0x0EUL)
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#define CACHE_ARCHITECTURE(x) (((x) >> 24) & 0x01)
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#define CACHE_ARCHITECTURE_UNIFIED (0UL)
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#define CACHE_ARCHITECTURE_SEPARATE (1UL)
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/// Defines the structure of the CSSELR (Cache Size Selection) register
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typedef union {
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struct {
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UINT32 InD :1; ///< Instruction not Data bit
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UINT32 Level :3; ///< Cache level (zero based)
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UINT32 TnD :1; ///< Allocation not Data bit
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UINT32 Reserved :27; ///< Reserved, RES0
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} Bits; ///< Bitfield definition of the register
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UINT32 Data; ///< The entire 32-bit value
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} CSSELR_DATA;
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/// The cache type values for the InD field of the CSSELR register
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typedef enum
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{
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/// Select the data or unified cache
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CsselrCacheTypeDataOrUnified = 0,
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/// Select the instruction cache
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CsselrCacheTypeInstruction,
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CsselrCacheTypeMax
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} CSSELR_CACHE_TYPE;
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/// Defines the structure of the CCSIDR (Current Cache Size ID) register
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typedef union {
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struct {
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UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4)
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UINT64 Associativity :10; ///< Associativity - 1
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UINT64 NumSets :15; ///< Number of sets in the cache -1
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UINT64 Unknown :4; ///< Reserved, UNKNOWN
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UINT64 Reserved :32; ///< Reserved, RES0
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} BitsNonCcidx; ///< Bitfield definition of the register when FEAT_CCIDX is not supported.
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struct {
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UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4)
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UINT64 Associativity :21; ///< Associativity - 1
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UINT64 Reserved1 :8; ///< Reserved, RES0
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UINT64 NumSets :24; ///< Number of sets in the cache -1
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UINT64 Reserved2 :8; ///< Reserved, RES0
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} BitsCcidxAA64; ///< Bitfield definition of the register when FEAT_IDX is supported.
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struct {
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UINT64 LineSize : 3;
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UINT64 Associativity : 21;
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UINT64 Reserved : 8;
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UINT64 Unallocated : 32;
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} BitsCcidxAA32;
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UINT64 Data; ///< The entire 64-bit value
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} CCSIDR_DATA;
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/// Defines the structure of the AARCH32 CCSIDR2 register.
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typedef union {
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struct {
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UINT32 NumSets :24; ///< Number of sets in the cache - 1
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UINT32 Reserved :8; ///< Reserved, RES0
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} Bits; ///< Bitfield definition of the register
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UINT32 Data; ///< The entire 32-bit value
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} CCSIDR2_DATA;
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/** Defines the structure of the CLIDR (Cache Level ID) register.
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*
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* The lower 32 bits are the same for both AARCH32 and AARCH64
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* so we can use the same structure for both.
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**/
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typedef union {
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struct {
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UINT32 Ctype1 : 3; ///< Level 1 cache type
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UINT32 Ctype2 : 3; ///< Level 2 cache type
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UINT32 Ctype3 : 3; ///< Level 3 cache type
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UINT32 Ctype4 : 3; ///< Level 4 cache type
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UINT32 Ctype5 : 3; ///< Level 5 cache type
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UINT32 Ctype6 : 3; ///< Level 6 cache type
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UINT32 Ctype7 : 3; ///< Level 7 cache type
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UINT32 LoUIS : 3; ///< Level of Unification Inner Shareable
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UINT32 LoC : 3; ///< Level of Coherency
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UINT32 LoUU : 3; ///< Level of Unification Uniprocessor
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UINT32 Icb : 3; ///< Inner Cache Boundary
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} Bits; ///< Bitfield definition of the register
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UINT32 Data; ///< The entire 32-bit value
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} CLIDR_DATA;
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/// The cache types reported in the CLIDR register.
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typedef enum {
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/// No cache is present
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ClidrCacheTypeNone = 0,
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/// There is only an instruction cache
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ClidrCacheTypeInstructionOnly,
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/// There is only a data cache
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ClidrCacheTypeDataOnly,
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/// There are separate data and instruction caches
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ClidrCacheTypeSeparate,
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/// There is a unified cache
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ClidrCacheTypeUnified,
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ClidrCacheTypeMax
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} CLIDR_CACHE_TYPE;
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#define CLIDR_GET_CACHE_TYPE(x, level) ((x >> (3 * (level))) & 0b111)
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VOID
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CPSRMaskInsert (
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IN UINT32 Mask,
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IN UINT32 Value
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);
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UINT32
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CPSRRead (
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VOID
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);
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/** Reads the CCSIDR register for the specified cache.
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@param CSSELR The CSSELR cache selection register value.
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@return The contents of the CCSIDR_EL1 register for the specified cache, when in AARCH64 mode.
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Returns the contents of the CCSIDR register in AARCH32 mode.
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**/
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UINTN
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ReadCCSIDR (
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IN UINT32 CSSELR
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);
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/** Reads the CCSIDR2 for the specified cache.
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@param CSSELR The CSSELR cache selection register value
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@return The contents of the CCSIDR2 register for the specified cache.
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**/
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UINT32
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ReadCCSIDR2 (
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IN UINT32 CSSELR
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);
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UINT32
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ReadCLIDR (
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VOID
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);
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#endif // ARM_LIB_PRIVATE_H_
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