This patch fixes the following Ecc reported error: File header doesn't exist File header comment missing the ""Copyright"" Even though a copyright is present in the header file, the leading '*' char prevents the Ecc tool from detecting it. According to the edk2 coding specifcation, section 5.2.3 "File Heading", there should not be leading '*' char. Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
		
			
				
	
	
		
			73 lines
		
	
	
		
			1.6 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			73 lines
		
	
	
		
			1.6 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /** @file
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|   Main file supporting the transition to PEI Core in Normal World for Versatile Express
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| 
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|   Copyright (c) 2011, ARM Limited. All rights reserved.
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| 
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|   SPDX-License-Identifier: BSD-2-Clause-Patent
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| 
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| **/
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| #ifndef __PREPEICORE_H_
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| #define __PREPEICORE_H_
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| 
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| #include <Library/ArmLib.h>
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| #include <Library/ArmPlatformLib.h>
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| #include <Library/BaseMemoryLib.h>
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| #include <Library/DebugLib.h>
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| #include <Library/IoLib.h>
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| #include <Library/PcdLib.h>
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| 
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| #include <PiPei.h>
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| #include <Ppi/TemporaryRamSupport.h>
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| 
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| VOID
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| CreatePpiList (
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|   OUT UINTN                   *PpiListSize,
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|   OUT EFI_PEI_PPI_DESCRIPTOR  **PpiList
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|   );
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| 
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| EFI_STATUS
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| EFIAPI
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| PrePeiCoreTemporaryRamSupport (
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|   IN CONST EFI_PEI_SERVICES   **PeiServices,
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|   IN EFI_PHYSICAL_ADDRESS     TemporaryMemoryBase,
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|   IN EFI_PHYSICAL_ADDRESS     PermanentMemoryBase,
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|   IN UINTN                    CopySize
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|   );
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| 
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| VOID
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| SecSwitchStack (
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|   INTN    StackDelta
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|   );
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| 
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| // Vector Table for Pei Phase
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| VOID  PeiVectorTable (VOID);
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| 
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| VOID
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| EFIAPI
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| PrimaryMain (
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|   IN  EFI_PEI_CORE_ENTRY_POINT  PeiCoreEntryPoint
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|   );
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| 
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| /*
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|  * This is the main function for secondary cores. They loop around until a non Null value is written to
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|  * SYS_FLAGS register.The SYS_FLAGS register is platform specific.
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|  * Note:The secondary cores, while executing secondary_main, assumes that:
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|  *      : SGI 0 is configured as Non-secure interrupt
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|  *      : Priority Mask is configured to allow SGI 0
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|  *      : Interrupt Distributor and CPU interfaces are enabled
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|  *
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|  */
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| VOID
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| EFIAPI
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| SecondaryMain (
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|   IN UINTN MpId
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|   );
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| 
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| VOID
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| PeiCommonExceptionEntry (
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|   IN UINT32 Entry,
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|   IN UINTN LR
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|   );
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| 
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| #endif
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