f2cdb268ef
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2698 To enhance FSP silicon initialization flexibility an optional Multi-Phase API is introduced and FSP header needs update for new API offset. Also new SecCore module created for FspMultiPhaseSiInit API New ARCH_UPD introduced for enhancing FSP debug message flexibility now bootloader can pass its own debug handler function pointer and FSP will call the function to handle debug message. To support calling bootloader functions, a FspGlobalData field added to indicate if FSP needs to switch stack when FSP running on separate stack from bootloader. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
53 lines
1.1 KiB
INI
53 lines
1.1 KiB
INI
## @file
|
|
# Sec Core for FSP to support MultiPhase (SeparatePhase) SiInitialization.
|
|
#
|
|
# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
|
|
#
|
|
# SPDX-License-Identifier: BSD-2-Clause-Patent
|
|
#
|
|
##
|
|
|
|
[Defines]
|
|
INF_VERSION = 0x00010005
|
|
BASE_NAME = Fsp22SecCoreS
|
|
FILE_GUID = DF0FCD70-264A-40BF-BBD4-06C76DB19CB1
|
|
MODULE_TYPE = SEC
|
|
VERSION_STRING = 1.0
|
|
|
|
#
|
|
# The following information is for reference only and not required by the build tools.
|
|
#
|
|
# VALID_ARCHITECTURES = IA32
|
|
#
|
|
|
|
[Sources]
|
|
SecFspApiChk.c
|
|
SecFsp.h
|
|
|
|
[Sources.IA32]
|
|
Ia32/Stack.nasm
|
|
Ia32/Fsp22ApiEntryS.nasm
|
|
Ia32/FspApiEntryCommon.nasm
|
|
Ia32/FspHelper.nasm
|
|
|
|
[Binaries.Ia32]
|
|
RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC
|
|
|
|
[Packages]
|
|
MdePkg/MdePkg.dec
|
|
IntelFsp2Pkg/IntelFsp2Pkg.dec
|
|
|
|
[LibraryClasses]
|
|
BaseMemoryLib
|
|
DebugLib
|
|
BaseLib
|
|
PciCf8Lib
|
|
SerialPortLib
|
|
FspSwitchStackLib
|
|
FspCommonLib
|
|
FspSecPlatformLib
|
|
|
|
[Ppis]
|
|
gEfiTemporaryRamSupportPpiGuid ## PRODUCES
|
|
|