86094561f6
https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
61 lines
1.3 KiB
C
61 lines
1.3 KiB
C
/** @file
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The internal header file that declared a data structure that is shared
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between the MM IPL and the MM Core.
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Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2016 - 2018, ARM Limited. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _STANDALONE_MM_CORE_PRIVATE_DATA_H_
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#define _STANDALONE_MM_CORE_PRIVATE_DATA_H_
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#include <Guid/MmCoreData.h>
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//
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// Page management
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//
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typedef struct {
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LIST_ENTRY Link;
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UINTN NumberOfPages;
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} FREE_PAGE_LIST;
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extern LIST_ENTRY mMmMemoryMap;
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//
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// Pool management
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//
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//
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// MIN_POOL_SHIFT must not be less than 5
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//
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#define MIN_POOL_SHIFT 6
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#define MIN_POOL_SIZE (1 << MIN_POOL_SHIFT)
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//
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// MAX_POOL_SHIFT must not be less than EFI_PAGE_SHIFT - 1
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//
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#define MAX_POOL_SHIFT (EFI_PAGE_SHIFT - 1)
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#define MAX_POOL_SIZE (1 << MAX_POOL_SHIFT)
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//
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// MAX_POOL_INDEX are calculated by maximum and minimum pool sizes
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//
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#define MAX_POOL_INDEX (MAX_POOL_SHIFT - MIN_POOL_SHIFT + 1)
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typedef struct {
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UINTN Size;
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BOOLEAN Available;
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} POOL_HEADER;
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typedef struct {
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POOL_HEADER Header;
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LIST_ENTRY Link;
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} FREE_POOL_HEADER;
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extern LIST_ENTRY mMmPoolLists[MAX_POOL_INDEX];
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#endif
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