When SEV-SNP is active, the CPUID and Secrets memory range contains the information that is used during the VM boot. The content need to be persist across the kexec boot. Mark the memory range as Reserved in the EFI map so that guest OS or firmware does not use the range as a system RAM. Cc: Michael Roth <michael.roth@amd.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
125 lines
1.8 KiB
C
125 lines
1.8 KiB
C
/** @file
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Platform PEI module include file.
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Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PLATFORM_PEI_H_INCLUDED_
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#define _PLATFORM_PEI_H_INCLUDED_
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#include <IndustryStandard/E820.h>
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VOID
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AddIoMemoryBaseSizeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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UINT64 MemorySize
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);
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VOID
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AddIoMemoryRangeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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EFI_PHYSICAL_ADDRESS MemoryLimit
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);
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VOID
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AddMemoryBaseSizeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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UINT64 MemorySize
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);
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VOID
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AddMemoryRangeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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EFI_PHYSICAL_ADDRESS MemoryLimit
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);
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VOID
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AddReservedMemoryBaseSizeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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UINT64 MemorySize,
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BOOLEAN Cacheable
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);
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VOID
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AddressWidthInitialization (
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VOID
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);
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VOID
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Q35TsegMbytesInitialization (
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VOID
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);
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VOID
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Q35SmramAtDefaultSmbaseInitialization (
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VOID
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);
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EFI_STATUS
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PublishPeiMemory (
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VOID
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);
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UINT32
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GetSystemMemorySizeBelow4gb (
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VOID
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);
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VOID
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QemuUc32BaseInitialization (
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VOID
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);
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VOID
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InitializeRamRegions (
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VOID
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);
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EFI_STATUS
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PeiFvInitialization (
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VOID
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);
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VOID
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MemTypeInfoInitialization (
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VOID
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);
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VOID
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InstallFeatureControlCallback (
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VOID
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);
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VOID
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InstallClearCacheCallback (
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VOID
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);
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VOID
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AmdSevInitialize (
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VOID
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);
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extern EFI_BOOT_MODE mBootMode;
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VOID
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SevInitializeRam (
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VOID
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);
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extern BOOLEAN mS3Supported;
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extern UINT8 mPhysMemAddressWidth;
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extern UINT32 mMaxCpuCount;
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extern UINT16 mHostBridgeDevId;
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extern BOOLEAN mQ35SmramAtDefaultSmbase;
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extern UINT32 mQemuUc32Base;
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#endif // _PLATFORM_PEI_H_INCLUDED_
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