e3b8fd1185
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1477 There was unused keyword added in FspmArchConfigPpi.h header block and should be removed. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
54 lines
1.5 KiB
C
54 lines
1.5 KiB
C
/** @file
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Header file for FSP-M Arch Config PPI for Dispatch mode
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Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials are licensed and made available under
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the terms and conditions of the BSD License which accompanies this distribution.
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The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef _FSPM_ARCH_CONFIG_PPI_H_
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#define _FSPM_ARCH_CONFIG_PPI_H_
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#define FSPM_ARCH_CONFIG_PPI_REVISION 0x1
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///
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/// Global ID for the FSPM_ARCH_CONFIG_PPI.
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///
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#define FSPM_ARCH_CONFIG_GUID \
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{ \
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0x824d5a3a, 0xaf92, 0x4c0c, { 0x9f, 0x19, 0x19, 0x52, 0x6d, 0xca, 0x4a, 0xbb } \
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}
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///
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/// This PPI provides FSP-M Arch Config PPI.
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///
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typedef struct {
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///
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/// Revision of the structure
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///
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UINT8 Revision;
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UINT8 Reserved[3];
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///
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/// Pointer to the non-volatile storage (NVS) data buffer.
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/// If it is NULL it indicates the NVS data is not available.
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///
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VOID *NvsBufferPtr;
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///
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/// Size of memory to be reserved by FSP below "top
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/// of low usable memory" for bootloader usage.
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///
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UINT32 BootLoaderTolumSize;
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UINT8 Reserved1[4];
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} FSPM_ARCH_CONFIG_PPI;
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extern EFI_GUID gFspmArchConfigPpiGuid;
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#endif // _FSPM_ARCH_CONFIG_PPI_H_
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