9d510e61fc
https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
462 lines
15 KiB
C
462 lines
15 KiB
C
/** @file
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Ia32-specific functionality for DxeLoad.
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Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "DxeIpl.h"
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#include "VirtualMemory.h"
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#define IDT_ENTRY_COUNT 32
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typedef struct _X64_IDT_TABLE {
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//
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// Reserved 4 bytes preceding PeiService and IdtTable,
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// since IDT base address should be 8-byte alignment.
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//
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UINT32 Reserved;
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CONST EFI_PEI_SERVICES **PeiService;
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X64_IDT_GATE_DESCRIPTOR IdtTable[IDT_ENTRY_COUNT];
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} X64_IDT_TABLE;
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//
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// Global Descriptor Table (GDT)
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//
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GLOBAL_REMOVE_IF_UNREFERENCED IA32_GDT gGdtEntries[] = {
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/* selector { Global Segment Descriptor } */
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/* 0x00 */ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, //null descriptor
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/* 0x08 */ {{0xffff, 0, 0, 0x2, 1, 0, 1, 0xf, 0, 0, 1, 1, 0}}, //linear data segment descriptor
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/* 0x10 */ {{0xffff, 0, 0, 0xf, 1, 0, 1, 0xf, 0, 0, 1, 1, 0}}, //linear code segment descriptor
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/* 0x18 */ {{0xffff, 0, 0, 0x3, 1, 0, 1, 0xf, 0, 0, 1, 1, 0}}, //system data segment descriptor
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/* 0x20 */ {{0xffff, 0, 0, 0xa, 1, 0, 1, 0xf, 0, 0, 1, 1, 0}}, //system code segment descriptor
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/* 0x28 */ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, //spare segment descriptor
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/* 0x30 */ {{0xffff, 0, 0, 0x2, 1, 0, 1, 0xf, 0, 0, 1, 1, 0}}, //system data segment descriptor
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/* 0x38 */ {{0xffff, 0, 0, 0xa, 1, 0, 1, 0xf, 0, 1, 0, 1, 0}}, //system code segment descriptor
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/* 0x40 */ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, //spare segment descriptor
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};
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//
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// IA32 Gdt register
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//
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GLOBAL_REMOVE_IF_UNREFERENCED CONST IA32_DESCRIPTOR gGdt = {
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sizeof (gGdtEntries) - 1,
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(UINTN) gGdtEntries
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};
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GLOBAL_REMOVE_IF_UNREFERENCED IA32_DESCRIPTOR gLidtDescriptor = {
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sizeof (X64_IDT_GATE_DESCRIPTOR) * IDT_ENTRY_COUNT - 1,
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0
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};
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/**
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Allocates and fills in the Page Directory and Page Table Entries to
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establish a 4G page table.
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@param[in] StackBase Stack base address.
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@param[in] StackSize Stack size.
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@return The address of page table.
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**/
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UINTN
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Create4GPageTablesIa32Pae (
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IN EFI_PHYSICAL_ADDRESS StackBase,
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IN UINTN StackSize
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)
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{
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UINT8 PhysicalAddressBits;
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EFI_PHYSICAL_ADDRESS PhysicalAddress;
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UINTN IndexOfPdpEntries;
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UINTN IndexOfPageDirectoryEntries;
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UINT32 NumberOfPdpEntriesNeeded;
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PAGE_MAP_AND_DIRECTORY_POINTER *PageMap;
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PAGE_MAP_AND_DIRECTORY_POINTER *PageDirectoryPointerEntry;
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PAGE_TABLE_ENTRY *PageDirectoryEntry;
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UINTN TotalPagesNum;
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UINTN PageAddress;
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UINT64 AddressEncMask;
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//
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// Make sure AddressEncMask is contained to smallest supported address field
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//
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AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGING_1G_ADDRESS_MASK_64;
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PhysicalAddressBits = 32;
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//
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// Calculate the table entries needed.
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//
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NumberOfPdpEntriesNeeded = (UINT32) LShiftU64 (1, (PhysicalAddressBits - 30));
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TotalPagesNum = NumberOfPdpEntriesNeeded + 1;
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PageAddress = (UINTN) AllocatePageTableMemory (TotalPagesNum);
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ASSERT (PageAddress != 0);
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PageMap = (VOID *) PageAddress;
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PageAddress += SIZE_4KB;
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PageDirectoryPointerEntry = PageMap;
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PhysicalAddress = 0;
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for (IndexOfPdpEntries = 0; IndexOfPdpEntries < NumberOfPdpEntriesNeeded; IndexOfPdpEntries++, PageDirectoryPointerEntry++) {
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//
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// Each Directory Pointer entries points to a page of Page Directory entires.
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// So allocate space for them and fill them in in the IndexOfPageDirectoryEntries loop.
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//
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PageDirectoryEntry = (VOID *) PageAddress;
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PageAddress += SIZE_4KB;
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//
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// Fill in a Page Directory Pointer Entries
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//
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PageDirectoryPointerEntry->Uint64 = (UINT64) (UINTN) PageDirectoryEntry | AddressEncMask;
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PageDirectoryPointerEntry->Bits.Present = 1;
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for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PhysicalAddress += SIZE_2MB) {
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if ((IsNullDetectionEnabled () && PhysicalAddress == 0)
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|| ((PhysicalAddress < StackBase + StackSize)
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&& ((PhysicalAddress + SIZE_2MB) > StackBase))) {
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//
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// Need to split this 2M page that covers stack range.
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//
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Split2MPageTo4K (PhysicalAddress, (UINT64 *) PageDirectoryEntry, StackBase, StackSize);
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} else {
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//
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// Fill in the Page Directory entries
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//
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PageDirectoryEntry->Uint64 = (UINT64) PhysicalAddress | AddressEncMask;
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PageDirectoryEntry->Bits.ReadWrite = 1;
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PageDirectoryEntry->Bits.Present = 1;
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PageDirectoryEntry->Bits.MustBe1 = 1;
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}
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}
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}
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for (; IndexOfPdpEntries < 512; IndexOfPdpEntries++, PageDirectoryPointerEntry++) {
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ZeroMem (
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PageDirectoryPointerEntry,
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sizeof (PAGE_MAP_AND_DIRECTORY_POINTER)
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);
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}
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//
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// Protect the page table by marking the memory used for page table to be
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// read-only.
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//
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EnablePageTableProtection ((UINTN)PageMap, FALSE);
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return (UINTN) PageMap;
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}
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/**
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The function will check if IA32 PAE is supported.
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@retval TRUE IA32 PAE is supported.
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@retval FALSE IA32 PAE is not supported.
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**/
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BOOLEAN
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IsIa32PaeSupport (
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VOID
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)
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{
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UINT32 RegEax;
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UINT32 RegEdx;
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BOOLEAN Ia32PaeSupport;
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Ia32PaeSupport = FALSE;
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AsmCpuid (0x0, &RegEax, NULL, NULL, NULL);
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if (RegEax >= 0x1) {
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AsmCpuid (0x1, NULL, NULL, NULL, &RegEdx);
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if ((RegEdx & BIT6) != 0) {
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Ia32PaeSupport = TRUE;
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}
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}
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return Ia32PaeSupport;
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}
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/**
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The function will check if page table should be setup or not.
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@retval TRUE Page table should be created.
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@retval FALSE Page table should not be created.
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**/
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BOOLEAN
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ToBuildPageTable (
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VOID
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)
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{
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if (!IsIa32PaeSupport ()) {
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return FALSE;
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}
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if (IsNullDetectionEnabled ()) {
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return TRUE;
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}
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if (PcdGet8 (PcdHeapGuardPropertyMask) != 0) {
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return TRUE;
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}
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if (PcdGetBool (PcdCpuStackGuard)) {
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return TRUE;
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}
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if (IsEnableNonExecNeeded ()) {
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return TRUE;
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}
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return FALSE;
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}
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/**
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Transfers control to DxeCore.
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This function performs a CPU architecture specific operations to execute
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the entry point of DxeCore with the parameters of HobList.
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It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase.
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@param DxeCoreEntryPoint The entry point of DxeCore.
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@param HobList The start of HobList passed to DxeCore.
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**/
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VOID
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HandOffToDxeCore (
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IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint,
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IN EFI_PEI_HOB_POINTERS HobList
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)
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{
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EFI_STATUS Status;
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EFI_PHYSICAL_ADDRESS BaseOfStack;
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EFI_PHYSICAL_ADDRESS TopOfStack;
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UINTN PageTables;
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X64_IDT_GATE_DESCRIPTOR *IdtTable;
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UINTN SizeOfTemplate;
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VOID *TemplateBase;
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EFI_PHYSICAL_ADDRESS VectorAddress;
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UINT32 Index;
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X64_IDT_TABLE *IdtTableForX64;
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EFI_VECTOR_HANDOFF_INFO *VectorInfo;
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EFI_PEI_VECTOR_HANDOFF_INFO_PPI *VectorHandoffInfoPpi;
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BOOLEAN BuildPageTablesIa32Pae;
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if (IsNullDetectionEnabled ()) {
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ClearFirst4KPage (HobList.Raw);
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}
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Status = PeiServicesAllocatePages (EfiBootServicesData, EFI_SIZE_TO_PAGES (STACK_SIZE), &BaseOfStack);
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ASSERT_EFI_ERROR (Status);
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if (FeaturePcdGet(PcdDxeIplSwitchToLongMode)) {
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//
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// Compute the top of the stack we were allocated, which is used to load X64 dxe core.
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// Pre-allocate a 32 bytes which confroms to x64 calling convention.
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//
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// The first four parameters to a function are passed in rcx, rdx, r8 and r9.
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// Any further parameters are pushed on the stack. Furthermore, space (4 * 8bytes) for the
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// register parameters is reserved on the stack, in case the called function
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// wants to spill them; this is important if the function is variadic.
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//
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TopOfStack = BaseOfStack + EFI_SIZE_TO_PAGES (STACK_SIZE) * EFI_PAGE_SIZE - 32;
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//
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// x64 Calling Conventions requires that the stack must be aligned to 16 bytes
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//
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TopOfStack = (EFI_PHYSICAL_ADDRESS) (UINTN) ALIGN_POINTER (TopOfStack, 16);
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//
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// Load the GDT of Go64. Since the GDT of 32-bit Tiano locates in the BS_DATA
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// memory, it may be corrupted when copying FV to high-end memory
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//
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AsmWriteGdtr (&gGdt);
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//
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// Create page table and save PageMapLevel4 to CR3
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//
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PageTables = CreateIdentityMappingPageTables (BaseOfStack, STACK_SIZE);
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//
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// End of PEI phase signal
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//
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PERF_EVENT_SIGNAL_BEGIN (gEndOfPeiSignalPpi.Guid);
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Status = PeiServicesInstallPpi (&gEndOfPeiSignalPpi);
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PERF_EVENT_SIGNAL_END (gEndOfPeiSignalPpi.Guid);
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ASSERT_EFI_ERROR (Status);
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//
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// Paging might be already enabled. To avoid conflict configuration,
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// disable paging first anyway.
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//
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AsmWriteCr0 (AsmReadCr0 () & (~BIT31));
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AsmWriteCr3 (PageTables);
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//
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// Update the contents of BSP stack HOB to reflect the real stack info passed to DxeCore.
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//
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UpdateStackHob (BaseOfStack, STACK_SIZE);
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SizeOfTemplate = AsmGetVectorTemplatInfo (&TemplateBase);
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Status = PeiServicesAllocatePages (
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EfiBootServicesData,
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EFI_SIZE_TO_PAGES(sizeof (X64_IDT_TABLE) + SizeOfTemplate * IDT_ENTRY_COUNT),
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&VectorAddress
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);
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ASSERT_EFI_ERROR (Status);
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//
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// Store EFI_PEI_SERVICES** in the 4 bytes immediately preceding IDT to avoid that
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// it may not be gotten correctly after IDT register is re-written.
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//
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IdtTableForX64 = (X64_IDT_TABLE *) (UINTN) VectorAddress;
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IdtTableForX64->PeiService = GetPeiServicesTablePointer ();
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VectorAddress = (EFI_PHYSICAL_ADDRESS) (UINTN) (IdtTableForX64 + 1);
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IdtTable = IdtTableForX64->IdtTable;
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for (Index = 0; Index < IDT_ENTRY_COUNT; Index++) {
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IdtTable[Index].Ia32IdtEntry.Bits.GateType = 0x8e;
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IdtTable[Index].Ia32IdtEntry.Bits.Reserved_0 = 0;
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IdtTable[Index].Ia32IdtEntry.Bits.Selector = SYS_CODE64_SEL;
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IdtTable[Index].Ia32IdtEntry.Bits.OffsetLow = (UINT16) VectorAddress;
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IdtTable[Index].Ia32IdtEntry.Bits.OffsetHigh = (UINT16) (RShiftU64 (VectorAddress, 16));
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IdtTable[Index].Offset32To63 = (UINT32) (RShiftU64 (VectorAddress, 32));
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IdtTable[Index].Reserved = 0;
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CopyMem ((VOID *) (UINTN) VectorAddress, TemplateBase, SizeOfTemplate);
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AsmVectorFixup ((VOID *) (UINTN) VectorAddress, (UINT8) Index);
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VectorAddress += SizeOfTemplate;
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}
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gLidtDescriptor.Base = (UINTN) IdtTable;
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//
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// Disable interrupt of Debug timer, since new IDT table cannot handle it.
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//
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SaveAndSetDebugTimerInterrupt (FALSE);
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AsmWriteIdtr (&gLidtDescriptor);
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DEBUG ((
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DEBUG_INFO,
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"%a() Stack Base: 0x%lx, Stack Size: 0x%x\n",
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__FUNCTION__,
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BaseOfStack,
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STACK_SIZE
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));
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//
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// Go to Long Mode and transfer control to DxeCore.
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// Interrupts will not get turned on until the CPU AP is loaded.
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// Call x64 drivers passing in single argument, a pointer to the HOBs.
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//
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AsmEnablePaging64 (
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SYS_CODE64_SEL,
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DxeCoreEntryPoint,
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(EFI_PHYSICAL_ADDRESS)(UINTN)(HobList.Raw),
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0,
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TopOfStack
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);
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} else {
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//
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// Get Vector Hand-off Info PPI and build Guided HOB
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//
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Status = PeiServicesLocatePpi (
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&gEfiVectorHandoffInfoPpiGuid,
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0,
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NULL,
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(VOID **)&VectorHandoffInfoPpi
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);
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if (Status == EFI_SUCCESS) {
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DEBUG ((EFI_D_INFO, "Vector Hand-off Info PPI is gotten, GUIDed HOB is created!\n"));
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VectorInfo = VectorHandoffInfoPpi->Info;
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Index = 1;
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while (VectorInfo->Attribute != EFI_VECTOR_HANDOFF_LAST_ENTRY) {
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VectorInfo ++;
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Index ++;
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}
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BuildGuidDataHob (
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&gEfiVectorHandoffInfoPpiGuid,
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VectorHandoffInfoPpi->Info,
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sizeof (EFI_VECTOR_HANDOFF_INFO) * Index
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);
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}
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//
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// Compute the top of the stack we were allocated. Pre-allocate a UINTN
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// for safety.
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//
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TopOfStack = BaseOfStack + EFI_SIZE_TO_PAGES (STACK_SIZE) * EFI_PAGE_SIZE - CPU_STACK_ALIGNMENT;
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TopOfStack = (EFI_PHYSICAL_ADDRESS) (UINTN) ALIGN_POINTER (TopOfStack, CPU_STACK_ALIGNMENT);
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PageTables = 0;
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BuildPageTablesIa32Pae = ToBuildPageTable ();
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if (BuildPageTablesIa32Pae) {
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PageTables = Create4GPageTablesIa32Pae (BaseOfStack, STACK_SIZE);
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if (IsEnableNonExecNeeded ()) {
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EnableExecuteDisableBit();
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}
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}
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//
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// End of PEI phase signal
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//
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PERF_EVENT_SIGNAL_BEGIN (gEndOfPeiSignalPpi.Guid);
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Status = PeiServicesInstallPpi (&gEndOfPeiSignalPpi);
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PERF_EVENT_SIGNAL_END (gEndOfPeiSignalPpi.Guid);
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ASSERT_EFI_ERROR (Status);
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if (BuildPageTablesIa32Pae) {
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//
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// Paging might be already enabled. To avoid conflict configuration,
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// disable paging first anyway.
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//
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AsmWriteCr0 (AsmReadCr0 () & (~BIT31));
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AsmWriteCr3 (PageTables);
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//
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// Set Physical Address Extension (bit 5 of CR4).
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//
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AsmWriteCr4 (AsmReadCr4 () | BIT5);
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}
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//
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// Update the contents of BSP stack HOB to reflect the real stack info passed to DxeCore.
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//
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UpdateStackHob (BaseOfStack, STACK_SIZE);
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DEBUG ((
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DEBUG_INFO,
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"%a() Stack Base: 0x%lx, Stack Size: 0x%x\n",
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__FUNCTION__,
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BaseOfStack,
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STACK_SIZE
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));
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//
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// Transfer the control to the entry point of DxeCore.
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//
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if (BuildPageTablesIa32Pae) {
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AsmEnablePaging32 (
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(SWITCH_STACK_ENTRY_POINT)(UINTN)DxeCoreEntryPoint,
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HobList.Raw,
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NULL,
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(VOID *) (UINTN) TopOfStack
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);
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} else {
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SwitchStack (
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(SWITCH_STACK_ENTRY_POINT)(UINTN)DxeCoreEntryPoint,
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HobList.Raw,
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NULL,
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(VOID *) (UINTN) TopOfStack
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);
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}
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}
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}
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