9afcd48a94
Handle things differently when the detected host bridge matches the Cloud Hypervisor PCI host bridge identifier. Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Rob Bradford <robert.bradford@intel.com> Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
134 lines
3.4 KiB
C
134 lines
3.4 KiB
C
/** @file
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Provide constructor and GetTick for BaseRom instance of ACPI Timer Library
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Copyright (c) 2008 - 2012, Intel Corporation. All rights reserved.
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Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <Library/PciLib.h>
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#include <OvmfPlatforms.h>
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/**
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The constructor function enables ACPI IO space.
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If ACPI I/O space not enabled, this function will enable it.
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It will always return RETURN_SUCCESS.
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@retval EFI_SUCCESS The constructor always returns RETURN_SUCCESS.
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**/
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RETURN_STATUS
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EFIAPI
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AcpiTimerLibConstructor (
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VOID
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)
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{
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UINT16 HostBridgeDevId;
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UINTN Pmba;
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UINT32 PmbaAndVal;
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UINT32 PmbaOrVal;
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UINTN AcpiCtlReg;
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UINT8 AcpiEnBit;
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//
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// Query Host Bridge DID to determine platform type
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//
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HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
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switch (HostBridgeDevId) {
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case INTEL_82441_DEVICE_ID:
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Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
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PmbaAndVal = ~(UINT32)PIIX4_PMBA_MASK;
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PmbaOrVal = PIIX4_PMBA_VALUE;
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AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
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AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;
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break;
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case INTEL_Q35_MCH_DEVICE_ID:
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Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
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PmbaAndVal = ~(UINT32)ICH9_PMBASE_MASK;
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PmbaOrVal = ICH9_PMBASE_VALUE;
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AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);
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AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;
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break;
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case CLOUDHV_DEVICE_ID:
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return RETURN_SUCCESS;
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default:
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DEBUG ((
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DEBUG_ERROR,
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"%a: Unknown Host Bridge Device ID: 0x%04x\n",
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__FUNCTION__,
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HostBridgeDevId
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));
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ASSERT (FALSE);
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return RETURN_UNSUPPORTED;
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}
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//
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// Check to see if the Power Management Base Address is already enabled
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//
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if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {
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//
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// If the Power Management Base Address is not programmed,
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// then program it now.
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//
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PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal);
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//
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// Enable PMBA I/O port decodes
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//
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PciOr8 (AcpiCtlReg, AcpiEnBit);
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}
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return RETURN_SUCCESS;
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}
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/**
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Internal function to read the current tick counter of ACPI.
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Dynamically compute the address of the ACPI tick counter based on the
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properties of the underlying platform, to avoid relying on global variables.
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@return The tick counter read.
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**/
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UINT32
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InternalAcpiGetTimerTick (
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VOID
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)
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{
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UINT16 HostBridgeDevId;
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UINTN Pmba;
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//
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// Query Host Bridge DID to determine platform type
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//
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HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
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switch (HostBridgeDevId) {
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case INTEL_82441_DEVICE_ID:
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Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
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break;
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case INTEL_Q35_MCH_DEVICE_ID:
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Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
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break;
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case CLOUDHV_DEVICE_ID:
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return IoRead32 (CLOUDHV_ACPI_TIMER_IO_ADDRESS);
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default:
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DEBUG ((
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DEBUG_ERROR,
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"%a: Unknown Host Bridge Device ID: 0x%04x\n",
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__FUNCTION__,
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HostBridgeDevId
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));
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ASSERT (FALSE);
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return 0;
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}
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//
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// Read PMBA to read and return the current ACPI timer value.
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//
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return IoRead32 ((PciRead32 (Pmba) & ~PMBA_RTE) + ACPI_TIMER_OFFSET);
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}
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