f4c845e46b
With the following paging structure that maps [0, 2G] with ReadWrite
bit set.
PML4[0] --> PDPTE[0] --> PDE[0-255]
\-> PDPTE[1] --> PDE[0-255]
If ReadWrite bit is cleared in PML4[0] and PageTableMap() is called
to change [0, 2M] as writable, today's logic doesn't inherit the
parent entry's attributes when determining the child entry's
attributes. It just sets the PDPTE[0].PDE[0].ReadWrite bit.
But since the PML4[0].ReadWrite is 0, [0, 2M] is still read-only.
The change fixes the bug.
If the inheritable attributes in ParentPagingEntry conflicts with the
requested attributes, let the child entries take the parent attributes
and loosen the attribute in the parent entry.
E.g.: when PDPTE[0].ReadWrite = 0 but caller wants to map [0-2MB as
ReadWrite = 1 (PDE[0].ReadWrite = 1), we need to change
PDPTE[0].ReadWrite = 1 and let all PDE[0-255].ReadWrite = 0 first.
Then change PDE[0].ReadWrite = 1.
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
223 lines
8.1 KiB
C
223 lines
8.1 KiB
C
/** @file
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Internal header for CpuPageTableLib.
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Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef CPU_PAGE_TABLE_H_
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#define CPU_PAGE_TABLE_H_
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#include <Base.h>
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#include <Library/BaseLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/DebugLib.h>
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#include <Library/CpuPageTableLib.h>
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#define IA32_PE_BASE_ADDRESS_MASK_40 0xFFFFFFFFFF000ull
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#define IA32_PE_BASE_ADDRESS_MASK_39 0xFFFFFFFFFE000ull
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#define REGION_LENGTH(l) LShiftU64 (1, (l) * 9 + 3)
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typedef struct {
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UINT64 Present : 1; // 0 = Not present in memory, 1 = Present in memory
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UINT64 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write
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UINT64 UserSupervisor : 1; // 0 = Supervisor, 1=User
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UINT64 Reserved : 58;
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UINT64 Nx : 1; // No Execute bit
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} IA32_PAGE_COMMON_ENTRY;
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///
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/// Format of a non-leaf entry that references a page table entry
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///
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typedef union {
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struct {
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UINT64 Present : 1; // 0 = Not present in memory, 1 = Present in memory
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UINT64 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write
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UINT64 UserSupervisor : 1; // 0 = Supervisor, 1=User
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UINT64 WriteThrough : 1; // 0 = Write-Back caching, 1=Write-Through caching
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UINT64 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached
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UINT64 Accessed : 1; // 0 = Not accessed, 1 = Accessed (set by CPU)
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UINT64 Available0 : 1; // Ignored
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UINT64 MustBeZero : 1; // Must Be Zero
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UINT64 Available2 : 4; // Ignored
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UINT64 PageTableBaseAddress : 40; // Page Table Base Address
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UINT64 Available3 : 11; // Ignored
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UINT64 Nx : 1; // No Execute bit
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} Bits;
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UINT64 Uint64;
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} IA32_PAGE_NON_LEAF_ENTRY;
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#define IA32_PNLE_PAGE_TABLE_BASE_ADDRESS(pa) ((pa)->Uint64 & IA32_PE_BASE_ADDRESS_MASK_40)
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///
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/// Format of a PML5 Entry (PML5E) that References a PML4 Table
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///
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typedef IA32_PAGE_NON_LEAF_ENTRY IA32_PML5E;
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///
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/// Format of a PML4 Entry (PML4E) that References a Page-Directory-Pointer Table
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///
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typedef IA32_PAGE_NON_LEAF_ENTRY IA32_PML4E;
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///
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/// Format of a Page-Directory-Pointer-Table Entry (PDPTE) that References a Page Directory
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///
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typedef IA32_PAGE_NON_LEAF_ENTRY IA32_PDPTE;
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///
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/// Format of a Page-Directory Entry that References a Page Table
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///
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typedef IA32_PAGE_NON_LEAF_ENTRY IA32_PDE;
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///
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/// Format of a leaf entry that Maps a 1-Gbyte or 2-MByte Page
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///
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typedef union {
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struct {
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UINT64 Present : 1; // 0 = Not present in memory, 1 = Present in memory
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UINT64 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write
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UINT64 UserSupervisor : 1; // 0 = Supervisor, 1=User
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UINT64 WriteThrough : 1; // 0 = Write-Back caching, 1=Write-Through caching
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UINT64 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached
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UINT64 Accessed : 1; // 0 = Not accessed, 1 = Accessed (set by CPU)
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UINT64 Dirty : 1; // 0 = Not dirty, 1 = Dirty (set by CPU)
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UINT64 MustBeOne : 1; // Page Size. Must Be One
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UINT64 Global : 1; // 0 = Not global, 1 = Global (if CR4.PGE = 1)
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UINT64 Available1 : 3; // Ignored
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UINT64 Pat : 1; // PAT
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UINT64 PageTableBaseAddress : 39; // Page Table Base Address
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UINT64 Available3 : 7; // Ignored
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UINT64 ProtectionKey : 4; // Protection key
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UINT64 Nx : 1; // No Execute bit
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} Bits;
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UINT64 Uint64;
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} IA32_PAGE_LEAF_ENTRY_BIG_PAGESIZE;
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#define IA32_PLEB_PAGE_TABLE_BASE_ADDRESS(pa) ((pa)->Uint64 & IA32_PE_BASE_ADDRESS_MASK_39)
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///
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/// Format of a Page-Directory Entry that Maps a 2-MByte Page
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///
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typedef IA32_PAGE_LEAF_ENTRY_BIG_PAGESIZE IA32_PDE_2M;
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///
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/// Format of a Page-Directory-Pointer-Table Entry (PDPTE) that Maps a 1-GByte Page
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///
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typedef IA32_PAGE_LEAF_ENTRY_BIG_PAGESIZE IA32_PDPTE_1G;
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///
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/// Format of a Page-Table Entry that Maps a 4-KByte Page
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///
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typedef union {
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struct {
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UINT64 Present : 1; // 0 = Not present in memory, 1 = Present in memory
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UINT64 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write
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UINT64 UserSupervisor : 1; // 0 = Supervisor, 1=User
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UINT64 WriteThrough : 1; // 0 = Write-Back caching, 1=Write-Through caching
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UINT64 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached
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UINT64 Accessed : 1; // 0 = Not accessed, 1 = Accessed (set by CPU)
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UINT64 Dirty : 1; // 0 = Not dirty, 1 = Dirty (set by CPU)
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UINT64 Pat : 1; // PAT
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UINT64 Global : 1; // 0 = Not global, 1 = Global (if CR4.PGE = 1)
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UINT64 Available1 : 3; // Ignored
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UINT64 PageTableBaseAddress : 40; // Page Table Base Address
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UINT64 Available3 : 7; // Ignored
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UINT64 ProtectionKey : 4; // Protection key
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UINT64 Nx : 1; // No Execute bit
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} Bits;
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UINT64 Uint64;
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} IA32_PTE_4K;
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#define IA32_PTE4K_PAGE_TABLE_BASE_ADDRESS(pa) ((pa)->Uint64 & IA32_PE_BASE_ADDRESS_MASK_40)
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///
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/// Format of a Page-Directory-Pointer-Table Entry (PDPTE) that References a Page Directory (32bit PAE specific)
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///
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typedef union {
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struct {
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UINT64 Present : 1; // 0 = Not present in memory, 1 = Present in memory
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UINT64 MustBeZero : 2; // Must Be Zero
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UINT64 WriteThrough : 1; // 0 = Write-Back caching, 1=Write-Through caching
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UINT64 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached
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UINT64 MustBeZero2 : 4; // Must Be Zero
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UINT64 Available : 3; // Ignored
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UINT64 PageTableBaseAddress : 40; // Page Table Base Address
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UINT64 MustBeZero3 : 12; // Must Be Zero
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} Bits;
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UINT64 Uint64;
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} IA32_PDPTE_PAE;
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typedef union {
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IA32_PAGE_NON_LEAF_ENTRY Pnle; // To access Pml5, Pml4, Pdpte and Pde.
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IA32_PML5E Pml5;
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IA32_PML4E Pml4;
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IA32_PDPTE Pdpte;
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IA32_PDE Pde;
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IA32_PAGE_LEAF_ENTRY_BIG_PAGESIZE PleB; // to access Pdpte1G and Pde2M.
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IA32_PDPTE_1G Pdpte1G;
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IA32_PDE_2M Pde2M;
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IA32_PTE_4K Pte4K;
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IA32_PDPTE_PAE PdptePae;
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IA32_PAGE_COMMON_ENTRY Pce; // To access all common bits in above entries.
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UINT64 Uint64;
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UINTN Uintn;
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} IA32_PAGING_ENTRY;
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/**
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Return TRUE when the page table entry is a leaf entry that points to the physical address memory.
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Return FALSE when the page table entry is a non-leaf entry that points to the page table entries.
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@param[in] PagingEntry Pointer to the page table entry.
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@param[in] Level Page level where the page table entry resides in.
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@retval TRUE It's a leaf entry.
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@retval FALSE It's a non-leaf entry.
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**/
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BOOLEAN
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IsPle (
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IN IA32_PAGING_ENTRY *PagingEntry,
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IN UINTN Level
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);
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/**
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Return the attribute of a 2M/1G page table entry.
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@param[in] PleB Pointer to a 2M/1G page table entry.
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@param[in] ParentMapAttribute Pointer to the parent attribute.
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@return Attribute of the 2M/1G page table entry.
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**/
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UINT64
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PageTableLibGetPleBMapAttribute (
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IN IA32_PAGE_LEAF_ENTRY_BIG_PAGESIZE *PleB,
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IN IA32_MAP_ATTRIBUTE *ParentMapAttribute
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);
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/**
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Return the attribute of a non-leaf page table entry.
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@param[in] Pnle Pointer to a non-leaf page table entry.
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@param[in] ParentMapAttribute Pointer to the parent attribute.
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@return Attribute of the non-leaf page table entry.
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**/
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UINT64
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PageTableLibGetPnleMapAttribute (
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IN IA32_PAGE_NON_LEAF_ENTRY *Pnle,
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IN IA32_MAP_ATTRIBUTE *ParentMapAttribute
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);
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#endif
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