f6c5a29bb9
The function ArmReadMidr has been recently added, but that functionality was already present under other names such as Cp15IdCode and ArmMainIdCode. This change removes redundant code and moves the function to the Common library. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15276 6f19259b-4bc3-4df7-8a09-765794883524
201 lines
5.0 KiB
ArmAsm
201 lines
5.0 KiB
ArmAsm
#------------------------------------------------------------------------------
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#
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# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#------------------------------------------------------------------------------
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#include <AsmMacroIoLibV8.h>
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.text
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.align 3
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GCC_ASM_EXPORT (ArmReadMidr)
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GCC_ASM_EXPORT (ArmCacheInfo)
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GCC_ASM_EXPORT (ArmGetInterruptState)
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GCC_ASM_EXPORT (ArmGetFiqState)
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GCC_ASM_EXPORT (ArmGetTTBR0BaseAddress)
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GCC_ASM_EXPORT (ArmSetTTBR0)
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GCC_ASM_EXPORT (ArmGetTCR)
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GCC_ASM_EXPORT (ArmSetTCR)
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GCC_ASM_EXPORT (ArmGetMAIR)
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GCC_ASM_EXPORT (ArmSetMAIR)
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GCC_ASM_EXPORT (ArmWriteCpacr)
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GCC_ASM_EXPORT (ArmWriteAuxCr)
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GCC_ASM_EXPORT (ArmReadAuxCr)
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GCC_ASM_EXPORT (ArmInvalidateTlb)
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GCC_ASM_EXPORT (ArmUpdateTranslationTableEntry)
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GCC_ASM_EXPORT (ArmWriteCptr)
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GCC_ASM_EXPORT (ArmWriteScr)
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GCC_ASM_EXPORT (ArmWriteMVBar)
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GCC_ASM_EXPORT (ArmCallWFE)
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GCC_ASM_EXPORT (ArmCallSEV)
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#------------------------------------------------------------------------------
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.set DAIF_FIQ_BIT, (1 << 0)
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.set DAIF_IRQ_BIT, (1 << 1)
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ASM_PFX(ArmReadMidr):
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mrs x0, midr_el1 // Read from Main ID Register (MIDR)
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ret
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ASM_PFX(ArmCacheInfo):
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mrs x0, ctr_el0 // Read from Cache Type Regiter (CTR)
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ret
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ASM_PFX(ArmGetInterruptState):
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mrs x0, daif
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tst w0, #DAIF_IRQ_BIT // Check if IRQ is enabled. Enabled if 0.
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mov w0, #0
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mov w1, #1
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csel w0, w1, w0, ne
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ret
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ASM_PFX(ArmGetFiqState):
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mrs x0, daif
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tst w0, #DAIF_FIQ_BIT // Check if FIQ is enabled. Enabled if 0.
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mov w0, #0
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mov w1, #1
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csel w0, w1, w0, ne
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ret
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ASM_PFX(ArmWriteCpacr):
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msr cpacr_el1, x0 // Coprocessor Access Control Reg (CPACR)
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ret
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ASM_PFX(ArmWriteAuxCr):
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EL1_OR_EL2(x1)
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1:msr actlr_el1, x0 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3
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b 3f
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2:msr actlr_el2, x0 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3
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3:ret
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ASM_PFX(ArmReadAuxCr):
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EL1_OR_EL2(x1)
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1:mrs x0, actlr_el1 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3
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b 3f
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2:mrs x0, actlr_el2 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3
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3:ret
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ASM_PFX(ArmSetTTBR0):
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EL1_OR_EL2_OR_EL3(x1)
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1:msr ttbr0_el1, x0 // Translation Table Base Reg 0 (TTBR0)
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b 4f
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2:msr ttbr0_el2, x0 // Translation Table Base Reg 0 (TTBR0)
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b 4f
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3:msr ttbr0_el3, x0 // Translation Table Base Reg 0 (TTBR0)
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4:isb
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ret
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ASM_PFX(ArmGetTTBR0BaseAddress):
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EL1_OR_EL2(x1)
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1:mrs x0, ttbr0_el1
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b 3f
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2:mrs x0, ttbr0_el2
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3:LoadConstantToReg(0xFFFFFFFFFFFF, x1) /* Look at bottom 48 bits */
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and x0, x0, x1
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isb
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ret
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ASM_PFX(ArmGetTCR):
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EL1_OR_EL2_OR_EL3(x1)
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1:mrs x0, tcr_el1
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b 4f
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2:mrs x0, tcr_el2
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b 4f
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3:mrs x0, tcr_el3
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4:isb
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ret
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ASM_PFX(ArmSetTCR):
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EL1_OR_EL2_OR_EL3(x1)
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1:msr tcr_el1, x0
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b 4f
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2:msr tcr_el2, x0
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b 4f
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3:msr tcr_el3, x0
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4:isb
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ret
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ASM_PFX(ArmGetMAIR):
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EL1_OR_EL2_OR_EL3(x1)
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1:mrs x0, mair_el1
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b 4f
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2:mrs x0, mair_el2
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b 4f
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3:mrs x0, mair_el3
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4:isb
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ret
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ASM_PFX(ArmSetMAIR):
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EL1_OR_EL2_OR_EL3(x1)
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1:msr mair_el1, x0
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b 4f
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2:msr mair_el2, x0
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b 4f
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3:msr mair_el3, x0
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4:isb
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ret
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//
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//VOID
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//ArmUpdateTranslationTableEntry (
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// IN VOID *TranslationTableEntry // X0
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// IN VOID *MVA // X1
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// );
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ASM_PFX(ArmUpdateTranslationTableEntry):
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dc civac, x0 // Clean and invalidate data line
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dsb sy
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EL1_OR_EL2_OR_EL3(x0)
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1: tlbi vaae1, x1 // TLB Invalidate VA , EL1
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b 4f
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2: tlbi vae2, x1 // TLB Invalidate VA , EL2
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b 4f
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3: tlbi vae3, x1 // TLB Invalidate VA , EL3
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4: dsb sy
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isb
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ret
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ASM_PFX(ArmInvalidateTlb):
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EL1_OR_EL2_OR_EL3(x0)
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1: tlbi vmalle1
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b 4f
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2: tlbi alle2
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b 4f
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3: tlbi alle3
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4: dsb sy
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isb
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ret
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ASM_PFX(ArmWriteCptr):
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msr cptr_el3, x0 // EL3 Coprocessor Trap Reg (CPTR)
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ret
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ASM_PFX(ArmWriteScr):
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msr scr_el3, x0 // Secure configuration register EL3
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ret
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ASM_PFX(ArmWriteMVBar):
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msr vbar_el3, x0 // Excpetion Vector Base address for Monitor on EL3
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ret
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ASM_PFX(ArmCallWFE):
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wfe
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ret
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ASM_PFX(ArmCallSEV):
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sev
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ret
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ASM_FUNCTION_REMOVE_IF_UNREFERENCED
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