2281eb6f48
Problems have been encountered because some of the source files have execute permission set. This can cause git to report them as changed when they are checked out onto a file system with inherited permissions. This has been seen using Cygwin, MinGW and PowerShell Git. This patch makes no change to source file content, and only aims to correct the file modes/permissions. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19778 6f19259b-4bc3-4df7-8a09-765794883524
115 lines
2.5 KiB
NASM
115 lines
2.5 KiB
NASM
;------------------------------------------------------------------------------
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;
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; CopyMem() worker for ARM
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;
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; This file started out as C code that did 64 bit moves if the buffer was
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; 32-bit aligned, else it does a byte copy. It also does a byte copy for
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; any trailing bytes. Update using VSTM/SLDM to do 128 byte copies.
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;
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; Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
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; This program and the accompanying materials
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; are licensed and made available under the terms and conditions of the BSD License
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; which accompanies this distribution. The full text of the license may be found at
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; http://opensource.org/licenses/bsd-license.php
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;
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; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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;
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;------------------------------------------------------------------------------
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/**
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Copy Length bytes from Source to Destination. Overlap is OK.
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This implementation
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@param Destination Target of copy
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@param Source Place to copy from
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@param Length Number of bytes to copy
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@return Destination
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VOID *
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EFIAPI
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InternalMemCopyMem (
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OUT VOID *DestinationBuffer,
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IN CONST VOID *SourceBuffer,
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IN UINTN Length
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)
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**/
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INCLUDE AsmMacroExport.inc
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RVCT_ASM_EXPORT InternalMemCopyMem
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stmfd sp!, {r4, r9, lr}
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tst r0, #3
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mov r4, r0
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mov r9, r0
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mov ip, r2
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mov lr, r1
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movne r0, #0
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bne L4
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tst r1, #3
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movne r3, #0
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moveq r3, #1
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cmp r2, #127
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movls r0, #0
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andhi r0, r3, #1
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L4
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cmp r4, r1
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bcc L26
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bls L7
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rsb r3, r1, r4
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cmp ip, r3
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bcc L26
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cmp ip, #0
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beq L7
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add r9, r4, ip
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add lr, ip, r1
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b L16
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L29
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sub ip, ip, #8
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cmp ip, #7
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ldrd r2, [lr, #-8]!
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movls r0, #0
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cmp ip, #0
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strd r2, [r9, #-8]!
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beq L7
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L16
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cmp r0, #0
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bne L29
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sub r3, lr, #1
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sub ip, ip, #1
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ldrb r3, [r3, #0]
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sub r2, r9, #1
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cmp ip, #0
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sub r9, r9, #1
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sub lr, lr, #1
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strb r3, [r2, #0]
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bne L16
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b L7
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L11
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ldrb r3, [lr], #1
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sub ip, ip, #1
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strb r3, [r9], #1
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L26
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cmp ip, #0
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beq L7
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L30
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cmp r0, #0
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beq L11
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sub ip, ip, #128 // 32
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cmp ip, #127 // 31
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vldm lr!, {d0-d15}
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movls r0, #0
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cmp ip, #0
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vstm r9!, {d0-d15}
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bne L30
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L7
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dsb
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mov r0, r4
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ldmfd sp!, {r4, r9, pc}
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END
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