2281eb6f48
Problems have been encountered because some of the source files have execute permission set. This can cause git to report them as changed when they are checked out onto a file system with inherited permissions. This has been seen using Cygwin, MinGW and PowerShell Git. This patch makes no change to source file content, and only aims to correct the file modes/permissions. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19778 6f19259b-4bc3-4df7-8a09-765794883524
79 lines
1.9 KiB
NASM
79 lines
1.9 KiB
NASM
;------------------------------------------------------------------------------
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;
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; SetMem() worker for ARM
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;
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; This file started out as C code that did 64 bit moves if the buffer was
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; 32-bit aligned, else it does a byte copy. It also does a byte copy for
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; any trailing bytes. Update to use VSTM/VLDM to do 128 byte writes.
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;
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; Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
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; This program and the accompanying materials
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; are licensed and made available under the terms and conditions of the BSD License
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; which accompanies this distribution. The full text of the license may be found at
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; http://opensource.org/licenses/bsd-license.php
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;
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; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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;
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/**
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Set Buffer to Value for Size bytes.
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@param Buffer Memory to set.
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@param Length Number of bytes to set
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@param Value Value of the set operation.
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@return Buffer
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VOID *
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EFIAPI
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InternalMemSetMem (
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OUT VOID *Buffer,
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IN UINTN Length,
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IN UINT8 Value
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)
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**/
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INCLUDE AsmMacroExport.inc
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RVCT_ASM_EXPORT InternalMemSetMem
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stmfd sp!, {lr}
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tst r0, #3
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movne r3, #0
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moveq r3, #1
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cmp r1, #127
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movls lr, #0
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andhi lr, r3, #1
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cmp lr, #0
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mov r12, r0
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bne L31
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L32
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mov r3, #0
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b L43
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L31
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vdup.8 q0,r2
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vmov q1,q0
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vmov q2,q0
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vmov q3,q0
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vmov q4,q0
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vmov q5,q0
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vmov q6,q0
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vmov q7,q0
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b L32
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L34
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cmp lr, #0
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streqb r2, [r12], #1
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subeq r1, r1, #1
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beq L43
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sub r1, r1, #128
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cmp r1, #127
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movls lr, r3
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vstm r12!, {d0-d15}
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L43
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cmp r1, #0
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bne L34
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ldmfd sp!, {pc}
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END
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