0aff49e20f
Section 5.1.16 ("PCIEXBAR -- PCI Express Register Range Base Address") in
Intel document #316966-002 (already referenced near the top of this header
file) describes the Q35 DRAM Controller register that configures the
memory-mapped PCI config space (also known as MMCONFIG, and ECAM /
Enhanced Configuration Access Method).
In this patch we add the macros we'll need later. We'll only support the
256 MB memory-mapped config space -- enough for buses [0, 255].
Cc: Gabriel Somlo <somlo@cmu.edu>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Marcel Apfelbaum <marcel@redhat.com>
Cc: Micha³ Zegan <webczat_200@poczta.onet.pl>
Ref: https://github.com/tianocore/edk2/issues/32
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Tested-by: Gabriel Somlo <somlo@cmu.edu>
Tested-by: Micha³ Zegan <webczat_200@poczta.onet.pl>
107 lines
2.9 KiB
C
107 lines
2.9 KiB
C
/** @file
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Various register numbers and value bits based on the following publications:
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- Intel(R) datasheet 316966-002
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- Intel(R) datasheet 316972-004
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Copyright (C) 2015, Red Hat, Inc.
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Copyright (c) 2014, Gabriel L. Somlo <somlo@cmu.edu>
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This program and the accompanying materials are licensed and made available
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under the terms and conditions of the BSD License which accompanies this
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distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
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WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef __Q35_MCH_ICH9_H__
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#define __Q35_MCH_ICH9_H__
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#include <Library/PciLib.h>
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//
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// Host Bridge Device ID (DID) value for Q35/MCH
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//
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#define INTEL_Q35_MCH_DEVICE_ID 0x29C0
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//
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// B/D/F/Type: 0/0/0/PCI
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//
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#define DRAMC_REGISTER_Q35(Offset) PCI_LIB_ADDRESS (0, 0, 0, (Offset))
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#define MCH_GGC 0x52
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#define MCH_GGC_IVD BIT1
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#define MCH_PCIEXBAR_LOW 0x60
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#define MCH_PCIEXBAR_LOWMASK 0x0FFFFFFF
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#define MCH_PCIEXBAR_BUS_FF 0
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#define MCH_PCIEXBAR_EN BIT0
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#define MCH_PCIEXBAR_HIGH 0x64
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#define MCH_PCIEXBAR_HIGHMASK 0xFFFFFFF0
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#define MCH_SMRAM 0x9D
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#define MCH_SMRAM_D_LCK BIT4
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#define MCH_SMRAM_G_SMRAME BIT3
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#define MCH_ESMRAMC 0x9E
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#define MCH_ESMRAMC_H_SMRAME BIT7
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#define MCH_ESMRAMC_E_SMERR BIT6
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#define MCH_ESMRAMC_SM_CACHE BIT5
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#define MCH_ESMRAMC_SM_L1 BIT4
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#define MCH_ESMRAMC_SM_L2 BIT3
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#define MCH_ESMRAMC_TSEG_8MB BIT2
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#define MCH_ESMRAMC_TSEG_2MB BIT1
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#define MCH_ESMRAMC_TSEG_1MB 0
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#define MCH_ESMRAMC_TSEG_MASK (BIT2 | BIT1)
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#define MCH_ESMRAMC_T_EN BIT0
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#define MCH_GBSM 0xA4
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#define MCH_GBSM_MB_SHIFT 20
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#define MCH_BGSM 0xA8
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#define MCH_BGSM_MB_SHIFT 20
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#define MCH_TSEGMB 0xAC
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#define MCH_TSEGMB_MB_SHIFT 20
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#define MCH_TOLUD 0xB0
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#define MCH_TOLUD_MB_SHIFT 4
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//
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// B/D/F/Type: 0/0x1f/0/PCI
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//
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#define POWER_MGMT_REGISTER_Q35(Offset) \
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PCI_LIB_ADDRESS (0, 0x1f, 0, (Offset))
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#define ICH9_PMBASE 0x40
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#define ICH9_PMBASE_MASK (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | \
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BIT10 | BIT9 | BIT8 | BIT7)
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#define ICH9_ACPI_CNTL 0x44
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#define ICH9_ACPI_CNTL_ACPI_EN BIT7
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#define ICH9_GEN_PMCON_1 0xA0
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#define ICH9_GEN_PMCON_1_SMI_LOCK BIT4
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#define ICH9_RCBA 0xF0
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#define ICH9_RCBA_EN BIT0
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//
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// IO ports
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//
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#define ICH9_APM_CNT 0xB2
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#define ICH9_APM_STS 0xB3
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//
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// IO ports relative to PMBASE
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//
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#define ICH9_PMBASE_OFS_SMI_EN 0x30
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#define ICH9_SMI_EN_APMC_EN BIT5
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#define ICH9_SMI_EN_GBL_SMI_EN BIT0
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#define ICH9_ROOT_COMPLEX_BASE 0xFED1C000
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#endif
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