9b6bbcdbfd
Changes for V4 ============== 1) Remove Unicode character from C source file 2) Move delete of QuarkSocPkg\QuarkNorthCluster\Binary\QuarkMicrocode from QuarkPlatformPkg commit to QuarkSocPkg commit Changes for V2 ============== 1) Sync with new APIs in SmmCpuFeaturesLib class 2) Use new generic PCI serial driver PciSioSerialDxe in MdeModulePkg 3) Remove PCI serial driver from QuarkSocPkg 4) Apply optimizations to MtrrLib from MtrrLib in UefiCpuPkg 5) Convert all UNI files to utf-8 6) Replace tabs with spaces and remove trailing spaces 7) Add License.txt Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Acked-by: Jordan Justen <jordan.l.justen@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19286 6f19259b-4bc3-4df7-8a09-765794883524
106 lines
3.2 KiB
C
106 lines
3.2 KiB
C
/** @file
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Lib function for Pei Quark South Cluster.
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Copyright (c) 2013-2015 Intel Corporation.
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include "CommonHeader.h"
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/**
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Program SVID/SID the same as VID/DID*
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**/
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EFI_STATUS
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EFIAPI
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InitializeIohSsvidSsid (
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IN UINT8 Bus,
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IN UINT8 Device,
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IN UINT8 Func
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)
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{
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UINTN Index;
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for (Index = 0; Index <= IOH_PCI_IOSF2AHB_0_MAX_FUNCS; Index++) {
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if (((Device == IOH_PCI_IOSF2AHB_1_DEV_NUM) && (Index >= IOH_PCI_IOSF2AHB_1_MAX_FUNCS))) {
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continue;
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}
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IohMmPci32(0, Bus, Device, Index, PCI_REG_SVID0) = IohMmPci32(0, Bus, Device, Index, PCI_REG_VID);
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}
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return EFI_SUCCESS;
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}
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/* Enable memory, io, and bus master for USB controller */
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VOID
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EFIAPI
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EnableUsbMemIoBusMaster (
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IN UINT8 UsbBusNumber
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)
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{
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UINT16 CmdReg;
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CmdReg = PciRead16 (PCI_LIB_ADDRESS (UsbBusNumber, IOH_USB_OHCI_DEVICE_NUMBER, IOH_OHCI_FUNCTION_NUMBER, PCI_REG_PCICMD));
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CmdReg = (UINT16) (CmdReg | EFI_PCI_COMMAND_MEMORY_SPACE | EFI_PCI_COMMAND_IO_SPACE | EFI_PCI_COMMAND_BUS_MASTER);
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PciWrite16 (PCI_LIB_ADDRESS (UsbBusNumber, IOH_USB_OHCI_DEVICE_NUMBER, IOH_OHCI_FUNCTION_NUMBER, PCI_REG_PCICMD), CmdReg);
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CmdReg = PciRead16 (PCI_LIB_ADDRESS (UsbBusNumber, IOH_USB_EHCI_DEVICE_NUMBER, IOH_EHCI_FUNCTION_NUMBER, PCI_REG_PCICMD));
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CmdReg = (UINT16) (CmdReg | EFI_PCI_COMMAND_MEMORY_SPACE | EFI_PCI_COMMAND_IO_SPACE | EFI_PCI_COMMAND_BUS_MASTER);
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PciWrite16 (PCI_LIB_ADDRESS (UsbBusNumber, IOH_USB_EHCI_DEVICE_NUMBER, IOH_EHCI_FUNCTION_NUMBER, PCI_REG_PCICMD), CmdReg);
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}
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/**
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Read south cluster GPIO input from Port A.
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**/
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UINT32
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EFIAPI
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ReadIohGpioValues (
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VOID
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)
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{
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UINT32 GipData;
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UINT32 GipAddr;
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UINT32 TempBarAddr;
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UINT16 SaveCmdReg;
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UINT32 SaveBarReg;
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TempBarAddr = (UINT32) PcdGet64(PcdIohGpioMmioBase);
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GipAddr = PCI_LIB_ADDRESS(
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PcdGet8 (PcdIohGpioBusNumber),
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PcdGet8 (PcdIohGpioDevNumber),
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PcdGet8 (PcdIohGpioFunctionNumber), 0);
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//
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// Save current settings for PCI CMD/BAR registers.
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//
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SaveCmdReg = PciRead16 (GipAddr + PCI_COMMAND_OFFSET);
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SaveBarReg = PciRead32 (GipAddr + PcdGet8 (PcdIohGpioBarRegister));
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DEBUG ((EFI_D_INFO, "SC GPIO temporary enable at %08X\n", TempBarAddr));
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// Use predefined tempory memory resource.
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PciWrite32 ( GipAddr + PcdGet8 (PcdIohGpioBarRegister), TempBarAddr);
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PciWrite8 ( GipAddr + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE);
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// Read GPIO configuration
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GipData = MmioRead32(TempBarAddr + GPIO_EXT_PORTA);
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//
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// Restore settings for PCI CMD/BAR registers.
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//
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PciWrite32 ((GipAddr + PcdGet8 (PcdIohGpioBarRegister)), SaveBarReg);
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PciWrite16 (GipAddr + PCI_COMMAND_OFFSET, SaveCmdReg);
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// Only 8 bits valid.
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return GipData & 0x000000FF;
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}
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