f93f248a78
The idea is to remove the PCD PcdGicPrimaryCoreId to make the port easier (and also to allow changing the primary boot CPU without adding more platform specific code to UEFI). There is a risk the mailboxes contain garbage at boot time. But it should be easy enough to clear the mailboxes when starting UEFI to workaround this limitation. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14477 6f19259b-4bc3-4df7-8a09-765794883524
107 lines
3.6 KiB
C
107 lines
3.6 KiB
C
/** @file
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*
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* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#include "PrePi.h"
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#include <Library/ArmGicLib.h>
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#include <Ppi/ArmMpCoreInfo.h>
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VOID
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PrimaryMain (
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IN UINTN UefiMemoryBase,
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IN UINTN StacksBase,
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IN UINTN GlobalVariableBase,
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IN UINT64 StartTimeStamp
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)
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{
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// Check PcdGicPrimaryCoreId has been set in case the Primary Core is not the core 0 of Cluster 0
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DEBUG_CODE_BEGIN();
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if ((PcdGet32(PcdArmPrimaryCore) != 0) && (PcdGet32 (PcdGicPrimaryCoreId) == 0)) {
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DEBUG((EFI_D_WARN,"Warning: the PCD PcdGicPrimaryCoreId does not seem to be set up for the configuration.\n"));
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}
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DEBUG_CODE_END();
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// Enable the GIC Distributor
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ArmGicEnableDistributor(PcdGet32(PcdGicDistributorBase));
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// In some cases, the secondary cores are waiting for an SGI from the next stage boot loader to resume their initialization
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if (!FixedPcdGet32(PcdSendSgiToBringUpSecondaryCores)) {
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// Sending SGI to all the Secondary CPU interfaces
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ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));
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}
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PrePiMain (UefiMemoryBase, StacksBase, GlobalVariableBase, StartTimeStamp);
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// We must never return
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ASSERT(FALSE);
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}
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VOID
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SecondaryMain (
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IN UINTN MpId
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)
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{
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EFI_STATUS Status;
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ARM_MP_CORE_INFO_PPI *ArmMpCoreInfoPpi;
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UINTN Index;
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UINTN ArmCoreCount;
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ARM_CORE_INFO *ArmCoreInfoTable;
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UINT32 ClusterId;
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UINT32 CoreId;
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VOID (*SecondaryStart)(VOID);
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UINTN SecondaryEntryAddr;
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ClusterId = GET_CLUSTER_ID(MpId);
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CoreId = GET_CORE_ID(MpId);
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// On MP Core Platform we must implement the ARM MP Core Info PPI (gArmMpCoreInfoPpiGuid)
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Status = GetPlatformPpi (&gArmMpCoreInfoPpiGuid, (VOID**)&ArmMpCoreInfoPpi);
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ASSERT_EFI_ERROR (Status);
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ArmCoreCount = 0;
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Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);
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ASSERT_EFI_ERROR (Status);
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// Find the core in the ArmCoreTable
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for (Index = 0; Index < ArmCoreCount; Index++) {
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if ((ArmCoreInfoTable[Index].ClusterId == ClusterId) && (ArmCoreInfoTable[Index].CoreId == CoreId)) {
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break;
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}
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}
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// The ARM Core Info Table must define every core
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ASSERT (Index != ArmCoreCount);
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// Clear Secondary cores MailBox
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MmioWrite32 (ArmCoreInfoTable[Index].MailboxClearAddress, ArmCoreInfoTable[Index].MailboxClearValue);
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do {
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ArmCallWFI ();
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// Read the Mailbox
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SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress);
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// Acknowledge the interrupt and send End of Interrupt signal.
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ArmGicAcknowledgeInterrupt (PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase), NULL, NULL);
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} while (SecondaryEntryAddr == 0);
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// Jump to secondary core entry point.
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SecondaryStart = (VOID (*)())SecondaryEntryAddr;
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SecondaryStart();
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// The secondaries shouldn't reach here
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ASSERT(FALSE);
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}
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