f97ab1bbf4
The ARM architecture does not allow the actual geometries of the caches to be inferred from the CCSIDR cache info system register, since the geometry it reports is intended for performing cache maintenance by set/way and nothing else. Since the ArmLib cache info routines are based solely on CCSIDR contents, they should not be used. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18753 6f19259b-4bc3-4df7-8a09-765794883524
73 lines
1.3 KiB
C
73 lines
1.3 KiB
C
/** @file
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Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <Base.h>
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#include <Library/ArmLib.h>
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#include <Library/DebugLib.h>
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#include <Library/PcdLib.h>
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#include "ArmLibPrivate.h"
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VOID
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EFIAPI
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ArmSetAuxCrBit (
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IN UINT32 Bits
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)
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{
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UINT32 val = ArmReadAuxCr();
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val |= Bits;
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ArmWriteAuxCr(val);
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}
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VOID
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EFIAPI
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ArmUnsetAuxCrBit (
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IN UINT32 Bits
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)
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{
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UINT32 val = ArmReadAuxCr();
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val &= ~Bits;
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ArmWriteAuxCr(val);
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}
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//
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// Helper functions for accessing CPUACTLR
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//
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VOID
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EFIAPI
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ArmSetCpuActlrBit (
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IN UINTN Bits
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)
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{
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UINTN Value;
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Value = ArmReadCpuActlr ();
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Value |= Bits;
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ArmWriteCpuActlr (Value);
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}
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VOID
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EFIAPI
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ArmUnsetCpuActlrBit (
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IN UINTN Bits
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)
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{
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UINTN Value;
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Value = ArmReadCpuActlr ();
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Value &= ~Bits;
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ArmWriteCpuActlr (Value);
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}
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