375683654d
The Generic ACPI for Arm Components 1.0 Platform Design
Document, s2.6.4 "ASL code examples" provides information
to describe an Arm CoreLink CMN-600 Coherent Mesh Network
using an ASL definition block table.
The SSDT CMN-600 Table Generator uses the Configuration
Manager protocol to obtain the following information about
the CMN-600 device on the platform:
- the PERIPHBASE address location and address range;
- the ROOTNODEBASE address location;
- the number of Debug and Trace Controller (DTC)
and their respective interrupt number;
The CMN-600 mesh is described using the CM_ARM_CMN_600_INFO
and CM_ARM_EXTENDED_INTERRUPT structures in the Configuration
Manager.
The SSDT CMN-600 Table generator:
- gets the CMN-600 hardware information
from the configuration manager.
- uses the AmlLib interfaces to parse the AML
template BLOB and construct an AML tree.
- uses the AmlLib to update:
- the "_UID" value;
- the address location and range of the PERIPHBASE;
- the address location of the ROOTNODEBASE;
- the number of Debug and Trace Controller (DTC)
and their respective interrupt number;
- serializes the AML tree to an output buffer.
This output buffer contains the fixed-up AML code,
which is then installed as an ACPI SSDT table.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Co-authored-by: Sami Mujawar <sami.mujawar@arm.com>
Reviewed-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
883 lines
27 KiB
C
883 lines
27 KiB
C
/** @file
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Copyright (c) 2017 - 2020, Arm Limited. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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@par Glossary:
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- Cm or CM - Configuration Manager
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- Obj or OBJ - Object
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- Std or STD - Standard
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**/
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#ifndef ARM_NAMESPACE_OBJECTS_H_
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#define ARM_NAMESPACE_OBJECTS_H_
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#include <StandardNameSpaceObjects.h>
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#pragma pack(1)
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/** The EARM_OBJECT_ID enum describes the Object IDs
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in the ARM Namespace
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*/
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typedef enum ArmObjectID {
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EArmObjReserved, ///< 0 - Reserved
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EArmObjBootArchInfo, ///< 1 - Boot Architecture Info
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EArmObjCpuInfo, ///< 2 - CPU Info
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EArmObjPowerManagementProfileInfo, ///< 3 - Power Management Profile Info
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EArmObjGicCInfo, ///< 4 - GIC CPU Interface Info
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EArmObjGicDInfo, ///< 5 - GIC Distributor Info
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EArmObjGicMsiFrameInfo, ///< 6 - GIC MSI Frame Info
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EArmObjGicRedistributorInfo, ///< 7 - GIC Redistributor Info
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EArmObjGicItsInfo, ///< 8 - GIC ITS Info
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EArmObjSerialConsolePortInfo, ///< 9 - Serial Console Port Info
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EArmObjSerialDebugPortInfo, ///< 10 - Serial Debug Port Info
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EArmObjGenericTimerInfo, ///< 11 - Generic Timer Info
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EArmObjPlatformGTBlockInfo, ///< 12 - Platform GT Block Info
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EArmObjGTBlockTimerFrameInfo, ///< 13 - Generic Timer Block Frame Info
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EArmObjPlatformGenericWatchdogInfo, ///< 14 - Platform Generic Watchdog
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EArmObjPciConfigSpaceInfo, ///< 15 - PCI Configuration Space Info
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EArmObjHypervisorVendorIdentity, ///< 16 - Hypervisor Vendor Id
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EArmObjFixedFeatureFlags, ///< 17 - Fixed feature flags for FADT
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EArmObjItsGroup, ///< 18 - ITS Group
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EArmObjNamedComponent, ///< 19 - Named Component
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EArmObjRootComplex, ///< 20 - Root Complex
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EArmObjSmmuV1SmmuV2, ///< 21 - SMMUv1 or SMMUv2
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EArmObjSmmuV3, ///< 22 - SMMUv3
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EArmObjPmcg, ///< 23 - PMCG
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EArmObjGicItsIdentifierArray, ///< 24 - GIC ITS Identifier Array
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EArmObjIdMappingArray, ///< 25 - ID Mapping Array
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EArmObjSmmuInterruptArray, ///< 26 - SMMU Interrupt Array
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EArmObjProcHierarchyInfo, ///< 27 - Processor Hierarchy Info
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EArmObjCacheInfo, ///< 28 - Cache Info
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EArmObjProcNodeIdInfo, ///< 29 - Processor Node ID Info
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EArmObjCmRef, ///< 30 - CM Object Reference
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EArmObjMemoryAffinityInfo, ///< 31 - Memory Affinity Info
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EArmObjDeviceHandleAcpi, ///< 32 - Device Handle Acpi
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EArmObjDeviceHandlePci, ///< 33 - Device Handle Pci
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EArmObjGenericInitiatorAffinityInfo, ///< 34 - Generic Initiator Affinity
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EArmObjSerialPortInfo, ///< 35 - Generic Serial Port Info
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EArmObjCmn600Info, ///< 36 - CMN-600 Info
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EArmObjMax
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} EARM_OBJECT_ID;
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/** A structure that describes the
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ARM Boot Architecture flags.
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ID: EArmObjBootArchInfo
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*/
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typedef struct CmArmBootArchInfo {
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/** This is the ARM_BOOT_ARCH flags field of the FADT Table
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described in the ACPI Table Specification.
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*/
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UINT16 BootArchFlags;
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} CM_ARM_BOOT_ARCH_INFO;
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/** A structure that describes the
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Power Management Profile Information for the Platform.
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ID: EArmObjPowerManagementProfileInfo
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*/
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typedef struct CmArmPowerManagementProfileInfo {
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/** This is the Preferred_PM_Profile field of the FADT Table
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described in the ACPI Specification
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*/
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UINT8 PowerManagementProfile;
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} CM_ARM_POWER_MANAGEMENT_PROFILE_INFO;
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/** A structure that describes the
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GIC CPU Interface for the Platform.
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ID: EArmObjGicCInfo
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*/
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typedef struct CmArmGicCInfo {
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/// The GIC CPU Interface number.
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UINT32 CPUInterfaceNumber;
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/** The ACPI Processor UID. This must match the
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_UID of the CPU Device object information described
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in the DSDT/SSDT for the CPU.
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*/
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UINT32 AcpiProcessorUid;
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/** The flags field as described by the GICC structure
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in the ACPI Specification.
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*/
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UINT32 Flags;
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/** The parking protocol version field as described by
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the GICC structure in the ACPI Specification.
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*/
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UINT32 ParkingProtocolVersion;
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/** The Performance Interrupt field as described by
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the GICC structure in the ACPI Specification.
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*/
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UINT32 PerformanceInterruptGsiv;
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/** The CPU Parked address field as described by
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the GICC structure in the ACPI Specification.
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*/
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UINT64 ParkedAddress;
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/** The base address for the GIC CPU Interface
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as described by the GICC structure in the
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ACPI Specification.
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*/
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UINT64 PhysicalBaseAddress;
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/** The base address for GICV interface
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as described by the GICC structure in the
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ACPI Specification.
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*/
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UINT64 GICV;
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/** The base address for GICH interface
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as described by the GICC structure in the
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ACPI Specification.
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*/
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UINT64 GICH;
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/** The GICV maintenance interrupt
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as described by the GICC structure in the
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ACPI Specification.
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*/
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UINT32 VGICMaintenanceInterrupt;
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/** The base address for GICR interface
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as described by the GICC structure in the
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ACPI Specification.
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*/
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UINT64 GICRBaseAddress;
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/** The MPIDR for the CPU
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as described by the GICC structure in the
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ACPI Specification.
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*/
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UINT64 MPIDR;
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/** The Processor Power Efficiency class
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as described by the GICC structure in the
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ACPI Specification.
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*/
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UINT8 ProcessorPowerEfficiencyClass;
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/** Statistical Profiling Extension buffer overflow GSIV. Zero if
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unsupported by this processor. This field was introduced in
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ACPI 6.3 (MADT revision 5) and is therefore ignored when
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generating MADT revision 4 or lower.
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*/
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UINT16 SpeOverflowInterrupt;
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/** The proximity domain to which the logical processor belongs.
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This field is used to populate the GICC affinity structure
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in the SRAT table.
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*/
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UINT32 ProximityDomain;
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/** The clock domain to which the logical processor belongs.
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This field is used to populate the GICC affinity structure
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in the SRAT table.
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*/
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UINT32 ClockDomain;
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/** The GICC Affinity flags field as described by the GICC Affinity structure
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in the SRAT table.
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*/
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UINT32 AffinityFlags;
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} CM_ARM_GICC_INFO;
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/** A structure that describes the
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GIC Distributor information for the Platform.
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ID: EArmObjGicDInfo
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*/
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typedef struct CmArmGicDInfo {
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/// The Physical Base address for the GIC Distributor.
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UINT64 PhysicalBaseAddress;
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/** The global system interrupt
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number where this GIC Distributor's
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interrupt inputs start.
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*/
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UINT32 SystemVectorBase;
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/** The GIC version as described
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by the GICD structure in the
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ACPI Specification.
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*/
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UINT8 GicVersion;
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} CM_ARM_GICD_INFO;
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/** A structure that describes the
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GIC MSI Frame information for the Platform.
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ID: EArmObjGicMsiFrameInfo
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*/
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typedef struct CmArmGicMsiFrameInfo {
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/// The GIC MSI Frame ID
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UINT32 GicMsiFrameId;
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/// The Physical base address for the MSI Frame
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UINT64 PhysicalBaseAddress;
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/** The GIC MSI Frame flags
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as described by the GIC MSI frame
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structure in the ACPI Specification.
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*/
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UINT32 Flags;
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/// SPI Count used by this frame
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UINT16 SPICount;
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/// SPI Base used by this frame
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UINT16 SPIBase;
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} CM_ARM_GIC_MSI_FRAME_INFO;
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/** A structure that describes the
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GIC Redistributor information for the Platform.
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ID: EArmObjGicRedistributorInfo
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*/
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typedef struct CmArmGicRedistInfo {
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/** The physical address of a page range
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containing all GIC Redistributors.
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*/
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UINT64 DiscoveryRangeBaseAddress;
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/// Length of the GIC Redistributor Discovery page range
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UINT32 DiscoveryRangeLength;
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} CM_ARM_GIC_REDIST_INFO;
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/** A structure that describes the
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GIC Interrupt Translation Service information for the Platform.
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ID: EArmObjGicItsInfo
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*/
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typedef struct CmArmGicItsInfo {
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/// The GIC ITS ID
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UINT32 GicItsId;
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/// The physical address for the Interrupt Translation Service
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UINT64 PhysicalBaseAddress;
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/** The proximity domain to which the logical processor belongs.
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This field is used to populate the GIC ITS affinity structure
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in the SRAT table.
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*/
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UINT32 ProximityDomain;
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} CM_ARM_GIC_ITS_INFO;
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/** A structure that describes the
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Serial Port information for the Platform.
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ID: EArmObjSerialConsolePortInfo or
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EArmObjSerialDebugPortInfo or
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EArmObjSerialPortInfo
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*/
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typedef struct CmArmSerialPortInfo {
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/// The physical base address for the serial port
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UINT64 BaseAddress;
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/// The serial port interrupt
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UINT32 Interrupt;
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/// The serial port baud rate
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UINT64 BaudRate;
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/// The serial port clock
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UINT32 Clock;
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/// Serial Port subtype
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UINT16 PortSubtype;
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/// The Base address length
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UINT64 BaseAddressLength;
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} CM_ARM_SERIAL_PORT_INFO;
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/** A structure that describes the
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Generic Timer information for the Platform.
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ID: EArmObjGenericTimerInfo
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*/
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typedef struct CmArmGenericTimerInfo {
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/// The physical base address for the counter control frame
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UINT64 CounterControlBaseAddress;
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/// The physical base address for the counter read frame
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UINT64 CounterReadBaseAddress;
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/// The secure PL1 timer interrupt
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UINT32 SecurePL1TimerGSIV;
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/// The secure PL1 timer flags
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UINT32 SecurePL1TimerFlags;
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/// The non-secure PL1 timer interrupt
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UINT32 NonSecurePL1TimerGSIV;
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/// The non-secure PL1 timer flags
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UINT32 NonSecurePL1TimerFlags;
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/// The virtual timer interrupt
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UINT32 VirtualTimerGSIV;
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/// The virtual timer flags
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UINT32 VirtualTimerFlags;
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/// The non-secure PL2 timer interrupt
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UINT32 NonSecurePL2TimerGSIV;
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/// The non-secure PL2 timer flags
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UINT32 NonSecurePL2TimerFlags;
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/// GSIV for the virtual EL2 timer
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UINT32 VirtualPL2TimerGSIV;
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/// Flags for the virtual EL2 timer
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UINT32 VirtualPL2TimerFlags;
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} CM_ARM_GENERIC_TIMER_INFO;
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/** A structure that describes the
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Platform Generic Block Timer Frame information for the Platform.
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ID: EArmObjGTBlockTimerFrameInfo
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*/
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typedef struct CmArmGTBlockTimerFrameInfo {
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/// The Generic Timer frame number
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UINT8 FrameNumber;
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/// The physical base address for the CntBase block
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UINT64 PhysicalAddressCntBase;
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/// The physical base address for the CntEL0Base block
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UINT64 PhysicalAddressCntEL0Base;
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/// The physical timer interrupt
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UINT32 PhysicalTimerGSIV;
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/** The physical timer flags as described by the GT Block
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Timer frame Structure in the ACPI Specification.
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*/
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UINT32 PhysicalTimerFlags;
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/// The virtual timer interrupt
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UINT32 VirtualTimerGSIV;
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/** The virtual timer flags as described by the GT Block
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Timer frame Structure in the ACPI Specification.
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*/
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UINT32 VirtualTimerFlags;
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/** The common timer flags as described by the GT Block
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Timer frame Structure in the ACPI Specification.
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*/
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UINT32 CommonFlags;
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} CM_ARM_GTBLOCK_TIMER_FRAME_INFO;
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/** A structure that describes the
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Platform Generic Block Timer information for the Platform.
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ID: EArmObjPlatformGTBlockInfo
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*/
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typedef struct CmArmGTBlockInfo {
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/// The physical base address for the GT Block Timer structure
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UINT64 GTBlockPhysicalAddress;
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/// The number of timer frames implemented in the GT Block
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UINT32 GTBlockTimerFrameCount;
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/// Reference token for the GT Block timer frame list
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CM_OBJECT_TOKEN GTBlockTimerFrameToken;
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} CM_ARM_GTBLOCK_INFO;
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/** A structure that describes the
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SBSA Generic Watchdog information for the Platform.
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ID: EArmObjPlatformGenericWatchdogInfo
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*/
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typedef struct CmArmGenericWatchdogInfo {
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/// The physical base address of the SBSA Watchdog control frame
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UINT64 ControlFrameAddress;
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/// The physical base address of the SBSA Watchdog refresh frame
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UINT64 RefreshFrameAddress;
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/// The watchdog interrupt
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UINT32 TimerGSIV;
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/** The flags for the watchdog as described by the SBSA watchdog
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structure in the ACPI specification.
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*/
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UINT32 Flags;
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} CM_ARM_GENERIC_WATCHDOG_INFO;
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/** A structure that describes the
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PCI Configuration Space information for the Platform.
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ID: EArmObjPciConfigSpaceInfo
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*/
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typedef struct CmArmPciConfigSpaceInfo {
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/// The physical base address for the PCI segment
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UINT64 BaseAddress;
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/// The PCI segment group number
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UINT16 PciSegmentGroupNumber;
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/// The start bus number
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UINT8 StartBusNumber;
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/// The end bus number
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UINT8 EndBusNumber;
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} CM_ARM_PCI_CONFIG_SPACE_INFO;
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/** A structure that describes the
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Hypervisor Vendor ID information for the Platform.
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ID: EArmObjHypervisorVendorIdentity
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*/
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typedef struct CmArmHypervisorVendorId {
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/// The hypervisor Vendor ID
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UINT64 HypervisorVendorId;
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} CM_ARM_HYPERVISOR_VENDOR_ID;
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/** A structure that describes the
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Fixed feature flags for the Platform.
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ID: EArmObjFixedFeatureFlags
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*/
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typedef struct CmArmFixedFeatureFlags {
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/// The Fixed feature flags
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UINT32 Flags;
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} CM_ARM_FIXED_FEATURE_FLAGS;
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/** A structure that describes the
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ITS Group node for the Platform.
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ID: EArmObjItsGroup
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*/
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typedef struct CmArmItsGroupNode {
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/// An unique token used to identify this object
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CM_OBJECT_TOKEN Token;
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/// The number of ITS identifiers in the ITS node
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UINT32 ItsIdCount;
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/// Reference token for the ITS identifier array
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CM_OBJECT_TOKEN ItsIdToken;
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} CM_ARM_ITS_GROUP_NODE;
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/** A structure that describes the
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GIC ITS Identifiers for an ITS Group node.
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ID: EArmObjGicItsIdentifierArray
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*/
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typedef struct CmArmGicItsIdentifier {
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/// The ITS Identifier
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UINT32 ItsId;
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} CM_ARM_ITS_IDENTIFIER;
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/** A structure that describes the
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Named component node for the Platform.
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ID: EArmObjNamedComponent
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*/
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typedef struct CmArmNamedComponentNode {
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/// An unique token used to identify this object
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CM_OBJECT_TOKEN Token;
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/// Number of ID mappings
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UINT32 IdMappingCount;
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/// Reference token for the ID mapping array
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CM_OBJECT_TOKEN IdMappingToken;
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/// Flags for the named component
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UINT32 Flags;
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/// Memory access properties : Cache coherent attributes
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UINT32 CacheCoherent;
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/// Memory access properties : Allocation hints
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UINT8 AllocationHints;
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/// Memory access properties : Memory access flags
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UINT8 MemoryAccessFlags;
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/// Memory access properties : Address size limit
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UINT8 AddressSizeLimit;
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/** ASCII Null terminated string with the full path to
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the entry in the namespace for this object.
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*/
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CHAR8* ObjectName;
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} CM_ARM_NAMED_COMPONENT_NODE;
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/** A structure that describes the
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Root complex node for the Platform.
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ID: EArmObjRootComplex
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*/
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typedef struct CmArmRootComplexNode {
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/// An unique token used to identify this object
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CM_OBJECT_TOKEN Token;
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/// Number of ID mappings
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UINT32 IdMappingCount;
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/// Reference token for the ID mapping array
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CM_OBJECT_TOKEN IdMappingToken;
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/// Memory access properties : Cache coherent attributes
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UINT32 CacheCoherent;
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/// Memory access properties : Allocation hints
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UINT8 AllocationHints;
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/// Memory access properties : Memory access flags
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UINT8 MemoryAccessFlags;
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/// ATS attributes
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UINT32 AtsAttribute;
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/// PCI segment number
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UINT32 PciSegmentNumber;
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/// Memory address size limit
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UINT8 MemoryAddressSize;
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} CM_ARM_ROOT_COMPLEX_NODE;
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/** A structure that describes the
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SMMUv1 or SMMUv2 node for the Platform.
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ID: EArmObjSmmuV1SmmuV2
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*/
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typedef struct CmArmSmmuV1SmmuV2Node {
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/// An unique token used to identify this object
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CM_OBJECT_TOKEN Token;
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/// Number of ID mappings
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UINT32 IdMappingCount;
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/// Reference token for the ID mapping array
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CM_OBJECT_TOKEN IdMappingToken;
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/// SMMU Base Address
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|
UINT64 BaseAddress;
|
|
/// Length of the memory range covered by the SMMU
|
|
UINT64 Span;
|
|
/// SMMU Model
|
|
UINT32 Model;
|
|
/// SMMU flags
|
|
UINT32 Flags;
|
|
|
|
/// Number of context interrupts
|
|
UINT32 ContextInterruptCount;
|
|
/// Reference token for the context interrupt array
|
|
CM_OBJECT_TOKEN ContextInterruptToken;
|
|
|
|
/// Number of PMU interrupts
|
|
UINT32 PmuInterruptCount;
|
|
/// Reference token for the PMU interrupt array
|
|
CM_OBJECT_TOKEN PmuInterruptToken;
|
|
|
|
/// GSIV of the SMMU_NSgIrpt interrupt
|
|
UINT32 SMMU_NSgIrpt;
|
|
/// SMMU_NSgIrpt interrupt flags
|
|
UINT32 SMMU_NSgIrptFlags;
|
|
/// GSIV of the SMMU_NSgCfgIrpt interrupt
|
|
UINT32 SMMU_NSgCfgIrpt;
|
|
/// SMMU_NSgCfgIrpt interrupt flags
|
|
UINT32 SMMU_NSgCfgIrptFlags;
|
|
} CM_ARM_SMMUV1_SMMUV2_NODE;
|
|
|
|
/** A structure that describes the
|
|
SMMUv3 node for the Platform.
|
|
|
|
ID: EArmObjSmmuV3
|
|
*/
|
|
typedef struct CmArmSmmuV3Node {
|
|
/// An unique token used to identify this object
|
|
CM_OBJECT_TOKEN Token;
|
|
/// Number of ID mappings
|
|
UINT32 IdMappingCount;
|
|
/// Reference token for the ID mapping array
|
|
CM_OBJECT_TOKEN IdMappingToken;
|
|
|
|
/// SMMU Base Address
|
|
UINT64 BaseAddress;
|
|
/// SMMU flags
|
|
UINT32 Flags;
|
|
/// VATOS address
|
|
UINT64 VatosAddress;
|
|
/// Model
|
|
UINT32 Model;
|
|
/// GSIV of the Event interrupt if SPI based
|
|
UINT32 EventInterrupt;
|
|
/// PRI Interrupt if SPI based
|
|
UINT32 PriInterrupt;
|
|
/// GERR interrupt if GSIV based
|
|
UINT32 GerrInterrupt;
|
|
/// Sync interrupt if GSIV based
|
|
UINT32 SyncInterrupt;
|
|
|
|
/// Proximity domain flag
|
|
UINT32 ProximityDomain;
|
|
/// Index into the array of ID mapping
|
|
UINT32 DeviceIdMappingIndex;
|
|
} CM_ARM_SMMUV3_NODE;
|
|
|
|
/** A structure that describes the
|
|
PMCG node for the Platform.
|
|
|
|
ID: EArmObjPmcg
|
|
*/
|
|
typedef struct CmArmPmcgNode {
|
|
/// An unique token used to identify this object
|
|
CM_OBJECT_TOKEN Token;
|
|
/// Number of ID mappings
|
|
UINT32 IdMappingCount;
|
|
/// Reference token for the ID mapping array
|
|
CM_OBJECT_TOKEN IdMappingToken;
|
|
|
|
/// Base Address for performance monitor counter group
|
|
UINT64 BaseAddress;
|
|
/// GSIV for the Overflow interrupt
|
|
UINT32 OverflowInterrupt;
|
|
/// Page 1 Base address
|
|
UINT64 Page1BaseAddress;
|
|
|
|
/// Reference token for the IORT node associated with this node
|
|
CM_OBJECT_TOKEN ReferenceToken;
|
|
} CM_ARM_PMCG_NODE;
|
|
|
|
/** A structure that describes the
|
|
ID Mappings for the Platform.
|
|
|
|
ID: EArmObjIdMappingArray
|
|
*/
|
|
typedef struct CmArmIdMapping {
|
|
/// Input base
|
|
UINT32 InputBase;
|
|
/// Number of input IDs
|
|
UINT32 NumIds;
|
|
/// Output Base
|
|
UINT32 OutputBase;
|
|
/// Reference token for the output node
|
|
CM_OBJECT_TOKEN OutputReferenceToken;
|
|
/// Flags
|
|
UINT32 Flags;
|
|
} CM_ARM_ID_MAPPING;
|
|
|
|
/** A structure that describes the Arm
|
|
Generic Interrupts.
|
|
*/
|
|
typedef struct CmArmGenericInterrupt {
|
|
/// Interrupt number
|
|
UINT32 Interrupt;
|
|
|
|
/// Flags
|
|
UINT32 Flags;
|
|
} CM_ARM_GENERIC_INTERRUPT;
|
|
|
|
/** A structure that describes the SMMU interrupts for the Platform.
|
|
|
|
Interrupt Interrupt number.
|
|
Flags Interrupt flags as defined for SMMU node.
|
|
|
|
ID: EArmObjSmmuInterruptArray
|
|
*/
|
|
typedef CM_ARM_GENERIC_INTERRUPT CM_ARM_SMMU_INTERRUPT;
|
|
|
|
/** A structure that describes the AML Extended Interrupts.
|
|
|
|
Interrupt Interrupt number.
|
|
Flags Interrupt flags as defined by the Interrupt
|
|
Vector Flags (Byte 3) of the Extended Interrupt
|
|
resource descriptor.
|
|
See EFI_ACPI_EXTENDED_INTERRUPT_FLAG_xxx in Acpi10.h
|
|
|
|
ID: EArmObjExtendedInterruptInfo
|
|
*/
|
|
typedef CM_ARM_GENERIC_INTERRUPT CM_ARM_EXTENDED_INTERRUPT;
|
|
|
|
/** A structure that describes the Processor Hierarchy Node (Type 0) in PPTT
|
|
|
|
ID: EArmObjProcHierarchyInfo
|
|
*/
|
|
typedef struct CmArmProcHierarchyInfo {
|
|
/// A unique token used to identify this object
|
|
CM_OBJECT_TOKEN Token;
|
|
/// Processor structure flags (ACPI 6.3 - January 2019, PPTT, Table 5-155)
|
|
UINT32 Flags;
|
|
/// Token for the parent CM_ARM_PROC_HIERARCHY_INFO object in the processor
|
|
/// topology. A value of CM_NULL_TOKEN means this node has no parent.
|
|
CM_OBJECT_TOKEN ParentToken;
|
|
/// Token of the associated CM_ARM_GICC_INFO object which has the
|
|
/// corresponding ACPI Processor ID. A value of CM_NULL_TOKEN means this
|
|
/// node represents a group of associated processors and it does not have an
|
|
/// associated GIC CPU interface.
|
|
CM_OBJECT_TOKEN GicCToken;
|
|
/// Number of resources private to this Node
|
|
UINT32 NoOfPrivateResources;
|
|
/// Token of the array which contains references to the resources private to
|
|
/// this CM_ARM_PROC_HIERARCHY_INFO instance. This field is ignored if
|
|
/// the NoOfPrivateResources is 0, in which case it is recommended to set
|
|
/// this field to CM_NULL_TOKEN.
|
|
CM_OBJECT_TOKEN PrivateResourcesArrayToken;
|
|
} CM_ARM_PROC_HIERARCHY_INFO;
|
|
|
|
/** A structure that describes the Cache Type Structure (Type 1) in PPTT
|
|
|
|
ID: EArmObjCacheInfo
|
|
*/
|
|
typedef struct CmArmCacheInfo {
|
|
/// A unique token used to identify this object
|
|
CM_OBJECT_TOKEN Token;
|
|
/// Reference token for the next level of cache that is private to the same
|
|
/// CM_ARM_PROC_HIERARCHY_INFO instance. A value of CM_NULL_TOKEN means this
|
|
/// entry represents the last cache level appropriate to the processor
|
|
/// hierarchy node structures using this entry.
|
|
CM_OBJECT_TOKEN NextLevelOfCacheToken;
|
|
/// Size of the cache in bytes
|
|
UINT32 Size;
|
|
/// Number of sets in the cache
|
|
UINT32 NumberOfSets;
|
|
/// Integer number of ways. The maximum associativity supported by
|
|
/// ACPI Cache type structure is limited to MAX_UINT8. However,
|
|
/// the maximum number of ways supported by the architecture is
|
|
/// PPTT_ARM_CCIDX_CACHE_ASSOCIATIVITY_MAX. Therfore this field
|
|
/// is 32-bit wide.
|
|
UINT32 Associativity;
|
|
/// Cache attributes (ACPI 6.3 - January 2019, PPTT, Table 5-156)
|
|
UINT8 Attributes;
|
|
/// Line size in bytes
|
|
UINT16 LineSize;
|
|
} CM_ARM_CACHE_INFO;
|
|
|
|
/** A structure that describes the ID Structure (Type 2) in PPTT
|
|
|
|
ID: EArmObjProcNodeIdInfo
|
|
*/
|
|
typedef struct CmArmProcNodeIdInfo {
|
|
/// A unique token used to identify this object
|
|
CM_OBJECT_TOKEN Token;
|
|
// Vendor ID (as described in ACPI ID registry)
|
|
UINT32 VendorId;
|
|
/// First level unique node ID
|
|
UINT64 Level1Id;
|
|
/// Second level unique node ID
|
|
UINT64 Level2Id;
|
|
/// Major revision of the node
|
|
UINT16 MajorRev;
|
|
/// Minor revision of the node
|
|
UINT16 MinorRev;
|
|
/// Spin revision of the node
|
|
UINT16 SpinRev;
|
|
} CM_ARM_PROC_NODE_ID_INFO;
|
|
|
|
/** A structure that describes a reference to another Configuration Manager
|
|
object.
|
|
|
|
This is useful for creating an array of reference tokens. The framework
|
|
can then query the configuration manager for these arrays using the
|
|
object ID EArmObjCmRef.
|
|
|
|
This can be used is to represent one-to-many relationships between objects.
|
|
|
|
ID: EArmObjCmRef
|
|
*/
|
|
typedef struct CmArmObjRef {
|
|
/// Token of the CM object being referenced
|
|
CM_OBJECT_TOKEN ReferenceToken;
|
|
} CM_ARM_OBJ_REF;
|
|
|
|
/** A structure that describes the Memory Affinity Structure (Type 1) in SRAT
|
|
|
|
ID: EArmObjMemoryAffinityInfo
|
|
*/
|
|
typedef struct CmArmMemoryAffinityInfo {
|
|
/// The proximity domain to which the "range of memory" belongs.
|
|
UINT32 ProximityDomain;
|
|
|
|
/// Base Address
|
|
UINT64 BaseAddress;
|
|
|
|
/// Length
|
|
UINT64 Length;
|
|
|
|
/// Flags
|
|
UINT32 Flags;
|
|
} CM_ARM_MEMORY_AFFINITY_INFO;
|
|
|
|
/** A structure that describes the ACPI Device Handle (Type 0) in the
|
|
Generic Initiator Affinity structure in SRAT
|
|
|
|
ID: EArmObjDeviceHandleAcpi
|
|
*/
|
|
typedef struct CmArmDeviceHandleAcpi {
|
|
/// Hardware ID
|
|
UINT64 Hid;
|
|
|
|
/// Unique Id
|
|
UINT32 Uid;
|
|
} CM_ARM_DEVICE_HANDLE_ACPI;
|
|
|
|
/** A structure that describes the PCI Device Handle (Type 1) in the
|
|
Generic Initiator Affinity structure in SRAT
|
|
|
|
ID: EArmObjDeviceHandlePci
|
|
*/
|
|
typedef struct CmArmDeviceHandlePci {
|
|
/// PCI Segment Number
|
|
UINT16 SegmentNumber;
|
|
|
|
/// PCI Bus Number - Max 256 busses (Bits 15:8 of BDF)
|
|
UINT8 BusNumber;
|
|
|
|
/// PCI Device Number - Max 32 devices (Bits 7:3 of BDF)
|
|
UINT8 DeviceNumber;
|
|
|
|
/// PCI Function Number - Max 8 functions (Bits 2:0 of BDF)
|
|
UINT8 FunctionNumber;
|
|
} CM_ARM_DEVICE_HANDLE_PCI;
|
|
|
|
/** A structure that describes the Generic Initiator Affinity structure in SRAT
|
|
|
|
ID: EArmObjGenericInitiatorAffinityInfo
|
|
*/
|
|
typedef struct CmArmGenericInitiatorAffinityInfo {
|
|
/// The proximity domain to which the generic initiator belongs.
|
|
UINT32 ProximityDomain;
|
|
|
|
/// Flags
|
|
UINT32 Flags;
|
|
|
|
/// Device Handle Type
|
|
UINT8 DeviceHandleType;
|
|
|
|
/// Reference Token for the Device Handle
|
|
CM_OBJECT_TOKEN DeviceHandleToken;
|
|
} CM_ARM_GENERIC_INITIATOR_AFFINITY_INFO;
|
|
|
|
/** A structure that describes the CMN-600 hardware.
|
|
|
|
ID: EArmObjCmn600Info
|
|
*/
|
|
typedef struct CmArmCmn600Info {
|
|
/// The PERIPHBASE address.
|
|
/// Corresponds to the Configuration Node Region (CFGR) base address.
|
|
UINT64 PeriphBaseAddress;
|
|
|
|
/// The PERIPHBASE address length.
|
|
/// Corresponds to the CFGR base address length.
|
|
UINT64 PeriphBaseAddressLength;
|
|
|
|
/// The ROOTNODEBASE address.
|
|
/// Corresponds to the Root node (ROOT) base address.
|
|
UINT64 RootNodeBaseAddress;
|
|
|
|
/// The Debug and Trace Logic Controller (DTC) count.
|
|
/// CMN-600 can have maximum 4 DTCs.
|
|
UINT8 DtcCount;
|
|
|
|
/// DTC Interrupt list.
|
|
/// The first interrupt resource descriptor pertains to
|
|
/// DTC[0], the second to DTC[1] and so on.
|
|
/// DtcCount determines the number of DTC Interrupts that
|
|
/// are populated. If DTC count is 2 then DtcInterrupt[2]
|
|
/// and DtcInterrupt[3] are ignored.
|
|
/// Note: The size of CM_ARM_CMN_600_INFO structure remains
|
|
/// constant and does not vary with the DTC count.
|
|
CM_ARM_EXTENDED_INTERRUPT DtcInterrupt[4];
|
|
} CM_ARM_CMN_600_INFO;
|
|
|
|
#pragma pack()
|
|
|
|
#endif // ARM_NAMESPACE_OBJECTS_H_
|