Updates debug macros in the package that have an imbalanced number of print specifiers to arguments. These changes try to preserve what was likely intended by the author. In cases information was missing due to the bug, the specifier may be removed since it was not previously accurately printing the expected value. Cc: Dandan Bi <dandan.bi@intel.com> Cc: Guomin Jiang <guomin.jiang@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
723 lines
22 KiB
C
723 lines
22 KiB
C
/** @file
|
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The NvmExpressPei driver is used to manage non-volatile memory subsystem
|
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which follows NVM Express specification at PEI phase.
|
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Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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|
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**/
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#include "NvmExpressPei.h"
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EFI_PEI_PPI_DESCRIPTOR mNvmeBlkIoPpiListTemplate = {
|
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EFI_PEI_PPI_DESCRIPTOR_PPI,
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&gEfiPeiVirtualBlockIoPpiGuid,
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NULL
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};
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EFI_PEI_PPI_DESCRIPTOR mNvmeBlkIo2PpiListTemplate = {
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(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
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&gEfiPeiVirtualBlockIo2PpiGuid,
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NULL
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};
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EFI_PEI_PPI_DESCRIPTOR mNvmeStorageSecurityPpiListTemplate = {
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(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
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&gEdkiiPeiStorageSecurityCommandPpiGuid,
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NULL
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};
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EFI_PEI_PPI_DESCRIPTOR mNvmePassThruPpiListTemplate = {
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(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
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&gEdkiiPeiNvmExpressPassThruPpiGuid,
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NULL
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};
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EFI_PEI_NOTIFY_DESCRIPTOR mNvmeEndOfPeiNotifyListTemplate = {
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(EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
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&gEfiEndOfPeiSignalPpiGuid,
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NvmePeimEndOfPei
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};
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EFI_PEI_NOTIFY_DESCRIPTOR mNvmeHostControllerNotify = {
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(EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
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&gEdkiiPeiNvmExpressHostControllerPpiGuid,
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NvmeHostControllerPpiInstallationCallback
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};
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EFI_PEI_NOTIFY_DESCRIPTOR mPciDevicePpiNotify = {
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(EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
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&gEdkiiPeiPciDevicePpiGuid,
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NvmePciDevicePpiInstallationCallback
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};
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/**
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Check if the specified Nvm Express device namespace is active, and then get the Identify
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Namespace data.
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@param[in,out] Private The pointer to the PEI_NVME_CONTROLLER_PRIVATE_DATA data structure.
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@param[in] NamespaceId The specified namespace identifier.
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@retval EFI_SUCCESS The specified namespace in the device is successfully enumerated.
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@return Others Error occurs when enumerating the namespace.
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**/
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EFI_STATUS
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EnumerateNvmeDevNamespace (
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IN OUT PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
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IN UINT32 NamespaceId
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)
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{
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EFI_STATUS Status;
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NVME_ADMIN_NAMESPACE_DATA *NamespaceData;
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PEI_NVME_NAMESPACE_INFO *NamespaceInfo;
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UINT32 DeviceIndex;
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UINT32 Lbads;
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UINT32 Flbas;
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UINT32 LbaFmtIdx;
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NamespaceData = (NVME_ADMIN_NAMESPACE_DATA *)AllocateZeroPool (sizeof (NVME_ADMIN_NAMESPACE_DATA));
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if (NamespaceData == NULL) {
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return EFI_OUT_OF_RESOURCES;
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}
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//
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// Identify Namespace
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//
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Status = NvmeIdentifyNamespace (
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Private,
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NamespaceId,
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NamespaceData
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);
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if (EFI_ERROR (Status)) {
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DEBUG ((DEBUG_ERROR, "%a: NvmeIdentifyNamespace fail, Status - %r\n", __FUNCTION__, Status));
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goto Exit;
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}
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//
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// Validate Namespace
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//
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if (NamespaceData->Ncap == 0) {
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DEBUG ((DEBUG_INFO, "%a: Namespace ID %d is an inactive one.\n", __FUNCTION__, NamespaceId));
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Status = EFI_DEVICE_ERROR;
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goto Exit;
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}
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DeviceIndex = Private->ActiveNamespaceNum;
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NamespaceInfo = &Private->NamespaceInfo[DeviceIndex];
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NamespaceInfo->NamespaceId = NamespaceId;
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NamespaceInfo->NamespaceUuid = NamespaceData->Eui64;
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NamespaceInfo->Controller = Private;
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Private->ActiveNamespaceNum++;
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//
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// Build BlockIo media structure
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//
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Flbas = NamespaceData->Flbas;
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LbaFmtIdx = Flbas & 0xF;
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//
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// Currently this NVME driver only suport Metadata Size == 0
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//
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if (NamespaceData->LbaFormat[LbaFmtIdx].Ms != 0) {
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DEBUG ((
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DEBUG_ERROR,
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"NVME IDENTIFY NAMESPACE [%d] Ms(%d) is not supported.\n",
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NamespaceId,
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NamespaceData->LbaFormat[LbaFmtIdx].Ms
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));
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Status = EFI_UNSUPPORTED;
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goto Exit;
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}
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Lbads = NamespaceData->LbaFormat[LbaFmtIdx].Lbads;
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NamespaceInfo->Media.InterfaceType = MSG_NVME_NAMESPACE_DP;
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NamespaceInfo->Media.RemovableMedia = FALSE;
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NamespaceInfo->Media.MediaPresent = TRUE;
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NamespaceInfo->Media.ReadOnly = FALSE;
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NamespaceInfo->Media.BlockSize = (UINT32)1 << Lbads;
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NamespaceInfo->Media.LastBlock = (EFI_PEI_LBA)NamespaceData->Nsze - 1;
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DEBUG ((
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DEBUG_INFO,
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"%a: Namespace ID %d - BlockSize = 0x%x, LastBlock = 0x%lx\n",
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__FUNCTION__,
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NamespaceId,
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NamespaceInfo->Media.BlockSize,
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NamespaceInfo->Media.LastBlock
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));
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Exit:
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if (NamespaceData != NULL) {
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FreePool (NamespaceData);
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}
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return Status;
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}
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/**
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Discover all Nvm Express device active namespaces.
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@param[in,out] Private The pointer to the PEI_NVME_CONTROLLER_PRIVATE_DATA data structure.
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@retval EFI_SUCCESS All the namespaces in the device are successfully enumerated.
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@return EFI_NOT_FOUND No active namespaces can be found.
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**/
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EFI_STATUS
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NvmeDiscoverNamespaces (
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IN OUT PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
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)
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{
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UINT32 NamespaceId;
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Private->ActiveNamespaceNum = 0;
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Private->NamespaceInfo = AllocateZeroPool (Private->ControllerData->Nn * sizeof (PEI_NVME_NAMESPACE_INFO));
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//
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// According to Nvm Express 1.1 spec Figure 82, the field 'Nn' of the identify
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// controller data defines the number of valid namespaces present for the
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// controller. Namespaces shall be allocated in order (starting with 1) and
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// packed sequentially.
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//
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for (NamespaceId = 1; NamespaceId <= Private->ControllerData->Nn; NamespaceId++) {
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//
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// For now, we do not care the return status. Since if a valid namespace is inactive,
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// error status will be returned. But we continue to enumerate other valid namespaces.
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//
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EnumerateNvmeDevNamespace (Private, NamespaceId);
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}
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if (Private->ActiveNamespaceNum == 0) {
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return EFI_NOT_FOUND;
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}
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return EFI_SUCCESS;
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}
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/**
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One notified function to cleanup the allocated resources at the end of PEI.
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@param[in] PeiServices Pointer to PEI Services Table.
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@param[in] NotifyDescriptor Pointer to the descriptor for the Notification
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event that caused this function to execute.
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@param[in] Ppi Pointer to the PPI data associated with this function.
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@retval EFI_SUCCESS The function completes successfully
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**/
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EFI_STATUS
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EFIAPI
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NvmePeimEndOfPei (
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IN EFI_PEI_SERVICES **PeiServices,
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IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
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IN VOID *Ppi
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)
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{
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PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
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Private = GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_NOTIFY (NotifyDescriptor);
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NvmeFreeDmaResource (Private);
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return EFI_SUCCESS;
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}
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/**
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Initialize and install PrivateData PPIs.
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@param[in] MmioBase MMIO base address of specific Nvme controller
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@param[in] DevicePath A pointer to the EFI_DEVICE_PATH_PROTOCOL
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structure.
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@param[in] DevicePathLength Length of the device path.
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@retval EFI_SUCCESS Nvme controller initialized and PPIs installed
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@retval others Failed to initialize Nvme controller
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**/
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EFI_STATUS
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NvmeInitPrivateData (
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IN UINTN MmioBase,
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IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
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IN UINTN DevicePathLength
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)
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{
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EFI_STATUS Status;
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EFI_BOOT_MODE BootMode;
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PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;
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EFI_PHYSICAL_ADDRESS DeviceAddress;
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DEBUG ((DEBUG_INFO, "%a: Enters.\n", __FUNCTION__));
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//
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// Get the current boot mode.
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//
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Status = PeiServicesGetBootMode (&BootMode);
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if (EFI_ERROR (Status)) {
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DEBUG ((DEBUG_ERROR, "%a: Fail to get the current boot mode.\n", __FUNCTION__));
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return Status;
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}
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//
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// Check validity of the device path of the NVM Express controller.
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//
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Status = NvmeIsHcDevicePathValid (DevicePath, DevicePathLength);
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if (EFI_ERROR (Status)) {
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DEBUG ((
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DEBUG_ERROR,
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"%a: The device path is invalid.\n",
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__FUNCTION__
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));
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return Status;
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}
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//
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// For S3 resume performance consideration, not all NVM Express controllers
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// will be initialized. The driver consumes the content within
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// S3StorageDeviceInitList LockBox to see if a controller will be skipped
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// during S3 resume.
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//
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if ((BootMode == BOOT_ON_S3_RESUME) &&
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(NvmeS3SkipThisController (DevicePath, DevicePathLength)))
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{
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DEBUG ((
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DEBUG_ERROR,
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"%a: skipped during S3.\n",
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__FUNCTION__
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));
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return EFI_SUCCESS;
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}
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//
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// Memory allocation for controller private data
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//
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Private = AllocateZeroPool (sizeof (PEI_NVME_CONTROLLER_PRIVATE_DATA));
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if (Private == NULL) {
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DEBUG ((
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DEBUG_ERROR,
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"%a: Fail to allocate private data.\n",
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|
__FUNCTION__
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));
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return EFI_OUT_OF_RESOURCES;
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}
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//
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// Memory allocation for transfer-related data
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//
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Status = IoMmuAllocateBuffer (
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NVME_MEM_MAX_PAGES,
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&Private->Buffer,
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&DeviceAddress,
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&Private->BufferMapping
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);
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if (EFI_ERROR (Status)) {
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DEBUG ((
|
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DEBUG_ERROR,
|
|
"%a: Fail to allocate DMA buffers.\n",
|
|
__FUNCTION__
|
|
));
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return Status;
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|
}
|
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|
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ASSERT (DeviceAddress == ((EFI_PHYSICAL_ADDRESS)(UINTN)Private->Buffer));
|
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DEBUG ((DEBUG_INFO, "%a: DMA buffer base at 0x%x\n", __FUNCTION__, Private->Buffer));
|
|
|
|
//
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// Initialize controller private data
|
|
//
|
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Private->Signature = NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE;
|
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Private->MmioBase = MmioBase;
|
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Private->DevicePathLength = DevicePathLength;
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Private->DevicePath = DevicePath;
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|
|
|
//
|
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// Initialize the NVME controller
|
|
//
|
|
Status = NvmeControllerInit (Private);
|
|
if (EFI_ERROR (Status)) {
|
|
DEBUG ((
|
|
DEBUG_ERROR,
|
|
"%a: Controller initialization fail with Status - %r.\n",
|
|
__FUNCTION__,
|
|
Status
|
|
));
|
|
NvmeFreeDmaResource (Private);
|
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return Status;
|
|
}
|
|
|
|
//
|
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// Enumerate the NVME namespaces on the controller
|
|
//
|
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Status = NvmeDiscoverNamespaces (Private);
|
|
if (EFI_ERROR (Status)) {
|
|
//
|
|
// No active namespace was found on the controller
|
|
//
|
|
DEBUG ((
|
|
DEBUG_ERROR,
|
|
"%a: Namespaces discovery fail with Status - %r.\n",
|
|
__FUNCTION__,
|
|
Status
|
|
));
|
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NvmeFreeDmaResource (Private);
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return Status;
|
|
}
|
|
|
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//
|
|
// Nvm Express Pass Thru PPI
|
|
//
|
|
Private->PassThruMode.Attributes = EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_PHYSICAL |
|
|
EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_LOGICAL |
|
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EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_CMD_SET_NVM;
|
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Private->PassThruMode.IoAlign = sizeof (UINTN);
|
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Private->PassThruMode.NvmeVersion = EDKII_PEI_NVM_EXPRESS_PASS_THRU_PPI_REVISION;
|
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Private->NvmePassThruPpi.Mode = &Private->PassThruMode;
|
|
Private->NvmePassThruPpi.GetDevicePath = NvmePassThruGetDevicePath;
|
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Private->NvmePassThruPpi.GetNextNameSpace = NvmePassThruGetNextNameSpace;
|
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Private->NvmePassThruPpi.PassThru = NvmePassThru;
|
|
CopyMem (
|
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&Private->NvmePassThruPpiList,
|
|
&mNvmePassThruPpiListTemplate,
|
|
sizeof (EFI_PEI_PPI_DESCRIPTOR)
|
|
);
|
|
Private->NvmePassThruPpiList.Ppi = &Private->NvmePassThruPpi;
|
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PeiServicesInstallPpi (&Private->NvmePassThruPpiList);
|
|
|
|
//
|
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// Block Io PPI
|
|
//
|
|
Private->BlkIoPpi.GetNumberOfBlockDevices = NvmeBlockIoPeimGetDeviceNo;
|
|
Private->BlkIoPpi.GetBlockDeviceMediaInfo = NvmeBlockIoPeimGetMediaInfo;
|
|
Private->BlkIoPpi.ReadBlocks = NvmeBlockIoPeimReadBlocks;
|
|
CopyMem (
|
|
&Private->BlkIoPpiList,
|
|
&mNvmeBlkIoPpiListTemplate,
|
|
sizeof (EFI_PEI_PPI_DESCRIPTOR)
|
|
);
|
|
Private->BlkIoPpiList.Ppi = &Private->BlkIoPpi;
|
|
|
|
Private->BlkIo2Ppi.Revision = EFI_PEI_RECOVERY_BLOCK_IO2_PPI_REVISION;
|
|
Private->BlkIo2Ppi.GetNumberOfBlockDevices = NvmeBlockIoPeimGetDeviceNo2;
|
|
Private->BlkIo2Ppi.GetBlockDeviceMediaInfo = NvmeBlockIoPeimGetMediaInfo2;
|
|
Private->BlkIo2Ppi.ReadBlocks = NvmeBlockIoPeimReadBlocks2;
|
|
CopyMem (
|
|
&Private->BlkIo2PpiList,
|
|
&mNvmeBlkIo2PpiListTemplate,
|
|
sizeof (EFI_PEI_PPI_DESCRIPTOR)
|
|
);
|
|
Private->BlkIo2PpiList.Ppi = &Private->BlkIo2Ppi;
|
|
PeiServicesInstallPpi (&Private->BlkIoPpiList);
|
|
|
|
//
|
|
// Check if the NVME controller supports the Security Receive/Send commands
|
|
//
|
|
if ((Private->ControllerData->Oacs & SECURITY_SEND_RECEIVE_SUPPORTED) != 0) {
|
|
DEBUG ((
|
|
DEBUG_INFO,
|
|
"%a: Security Security Command PPI will be produced.\n",
|
|
__FUNCTION__
|
|
));
|
|
Private->StorageSecurityPpi.Revision = EDKII_STORAGE_SECURITY_PPI_REVISION;
|
|
Private->StorageSecurityPpi.GetNumberofDevices = NvmeStorageSecurityGetDeviceNo;
|
|
Private->StorageSecurityPpi.GetDevicePath = NvmeStorageSecurityGetDevicePath;
|
|
Private->StorageSecurityPpi.ReceiveData = NvmeStorageSecurityReceiveData;
|
|
Private->StorageSecurityPpi.SendData = NvmeStorageSecuritySendData;
|
|
CopyMem (
|
|
&Private->StorageSecurityPpiList,
|
|
&mNvmeStorageSecurityPpiListTemplate,
|
|
sizeof (EFI_PEI_PPI_DESCRIPTOR)
|
|
);
|
|
Private->StorageSecurityPpiList.Ppi = &Private->StorageSecurityPpi;
|
|
PeiServicesInstallPpi (&Private->StorageSecurityPpiList);
|
|
}
|
|
|
|
CopyMem (
|
|
&Private->EndOfPeiNotifyList,
|
|
&mNvmeEndOfPeiNotifyListTemplate,
|
|
sizeof (EFI_PEI_NOTIFY_DESCRIPTOR)
|
|
);
|
|
PeiServicesNotifyPpi (&Private->EndOfPeiNotifyList);
|
|
|
|
return EFI_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
Initialize Nvme controller from fiven PCI_DEVICE_PPI.
|
|
|
|
@param[in] PciDevice Pointer to the PCI Device PPI instance.
|
|
|
|
@retval EFI_SUCCESS The function completes successfully
|
|
@retval Others Cannot initialize Nvme controller for given device
|
|
**/
|
|
EFI_STATUS
|
|
NvmeInitControllerDataFromPciDevice (
|
|
EDKII_PCI_DEVICE_PPI *PciDevice
|
|
)
|
|
{
|
|
EFI_STATUS Status;
|
|
PCI_TYPE00 PciData;
|
|
UINTN MmioBase;
|
|
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
|
|
UINTN DevicePathLength;
|
|
UINT64 EnabledPciAttributes;
|
|
UINT32 MmioBaseH;
|
|
|
|
//
|
|
// Now further check the PCI header: Base Class (offset 0x0B), Sub Class (offset 0x0A) and
|
|
// Programming Interface (offset 0x09). This controller should be an Nvme controller
|
|
//
|
|
Status = PciDevice->PciIo.Pci.Read (
|
|
&PciDevice->PciIo,
|
|
EfiPciIoWidthUint8,
|
|
PCI_CLASSCODE_OFFSET,
|
|
sizeof (PciData.Hdr.ClassCode),
|
|
PciData.Hdr.ClassCode
|
|
);
|
|
if (EFI_ERROR (Status)) {
|
|
return EFI_UNSUPPORTED;
|
|
}
|
|
|
|
if (!IS_PCI_NVMHCI (&PciData)) {
|
|
return EFI_UNSUPPORTED;
|
|
}
|
|
|
|
Status = PciDevice->PciIo.Attributes (
|
|
&PciDevice->PciIo,
|
|
EfiPciIoAttributeOperationSupported,
|
|
0,
|
|
&EnabledPciAttributes
|
|
);
|
|
if (EFI_ERROR (Status)) {
|
|
return EFI_UNSUPPORTED;
|
|
} else {
|
|
EnabledPciAttributes &= (UINT64)EFI_PCI_DEVICE_ENABLE;
|
|
Status = PciDevice->PciIo.Attributes (
|
|
&PciDevice->PciIo,
|
|
EfiPciIoAttributeOperationEnable,
|
|
EnabledPciAttributes,
|
|
NULL
|
|
);
|
|
if (EFI_ERROR (Status)) {
|
|
return EFI_UNSUPPORTED;
|
|
}
|
|
}
|
|
|
|
Status = PciDevice->PciIo.Pci.Read (
|
|
&PciDevice->PciIo,
|
|
EfiPciIoWidthUint32,
|
|
PCI_BASE_ADDRESSREG_OFFSET,
|
|
1,
|
|
&MmioBase
|
|
);
|
|
if (EFI_ERROR (Status)) {
|
|
return EFI_UNSUPPORTED;
|
|
}
|
|
|
|
switch (MmioBase & 0x07) {
|
|
case 0x0:
|
|
//
|
|
// Memory space for 32 bit bar address
|
|
//
|
|
MmioBase = MmioBase & 0xFFFFFFF0;
|
|
break;
|
|
case 0x4:
|
|
//
|
|
// For 64 bit bar address, read the high 32bits of this 64 bit bar
|
|
//
|
|
Status = PciDevice->PciIo.Pci.Read (
|
|
&PciDevice->PciIo,
|
|
EfiPciIoWidthUint32,
|
|
PCI_BASE_ADDRESSREG_OFFSET + 4,
|
|
1,
|
|
&MmioBaseH
|
|
);
|
|
//
|
|
// For 32 bit environment, high 32bits of the bar should be zero.
|
|
//
|
|
if ( EFI_ERROR (Status)
|
|
|| ((MmioBaseH != 0) && (sizeof (UINTN) == sizeof (UINT32))))
|
|
{
|
|
return EFI_UNSUPPORTED;
|
|
}
|
|
|
|
MmioBase = MmioBase & 0xFFFFFFF0;
|
|
MmioBase |= LShiftU64 ((UINT64)MmioBaseH, 32);
|
|
break;
|
|
default:
|
|
//
|
|
// Unknown bar type
|
|
//
|
|
return EFI_UNSUPPORTED;
|
|
}
|
|
|
|
DevicePathLength = GetDevicePathSize (PciDevice->DevicePath);
|
|
DevicePath = PciDevice->DevicePath;
|
|
|
|
Status = NvmeInitPrivateData (MmioBase, DevicePath, DevicePathLength);
|
|
if (EFI_ERROR (Status)) {
|
|
DEBUG ((
|
|
DEBUG_INFO,
|
|
"%a: Failed to init controller, with Status - %r\n",
|
|
__FUNCTION__,
|
|
Status
|
|
));
|
|
}
|
|
|
|
return EFI_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
Callback for EDKII_PCI_DEVICE_PPI installation.
|
|
|
|
@param[in] PeiServices Pointer to PEI Services Table.
|
|
@param[in] NotifyDescriptor Pointer to the descriptor for the Notification
|
|
event that caused this function to execute.
|
|
@param[in] Ppi Pointer to the PPI data associated with this function.
|
|
|
|
@retval EFI_SUCCESS The function completes successfully
|
|
@retval Others Cannot initialize Nvme controller from given PCI_DEVICE_PPI
|
|
|
|
**/
|
|
EFI_STATUS
|
|
EFIAPI
|
|
NvmePciDevicePpiInstallationCallback (
|
|
IN EFI_PEI_SERVICES **PeiServices,
|
|
IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
|
|
IN VOID *Ppi
|
|
)
|
|
{
|
|
EDKII_PCI_DEVICE_PPI *PciDevice;
|
|
|
|
PciDevice = (EDKII_PCI_DEVICE_PPI *)Ppi;
|
|
|
|
return NvmeInitControllerDataFromPciDevice (PciDevice);
|
|
}
|
|
|
|
/**
|
|
Initialize Nvme controller from EDKII_NVM_EXPRESS_HOST_CONTROLLER_PPI instance.
|
|
|
|
@param[in] NvmeHcPpi Pointer to the Nvme Host Controller PPI instance.
|
|
|
|
@retval EFI_SUCCESS PPI successfully installed.
|
|
**/
|
|
EFI_STATUS
|
|
NvmeInitControllerFromHostControllerPpi (
|
|
IN EDKII_NVM_EXPRESS_HOST_CONTROLLER_PPI *NvmeHcPpi
|
|
)
|
|
{
|
|
UINT8 Controller;
|
|
UINTN MmioBase;
|
|
UINTN DevicePathLength;
|
|
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
|
|
EFI_STATUS Status;
|
|
|
|
Controller = 0;
|
|
MmioBase = 0;
|
|
while (TRUE) {
|
|
Status = NvmeHcPpi->GetNvmeHcMmioBar (
|
|
NvmeHcPpi,
|
|
Controller,
|
|
&MmioBase
|
|
);
|
|
//
|
|
// When status is error, meant no controller is found
|
|
//
|
|
if (EFI_ERROR (Status)) {
|
|
break;
|
|
}
|
|
|
|
Status = NvmeHcPpi->GetNvmeHcDevicePath (
|
|
NvmeHcPpi,
|
|
Controller,
|
|
&DevicePathLength,
|
|
&DevicePath
|
|
);
|
|
if (EFI_ERROR (Status)) {
|
|
DEBUG ((
|
|
DEBUG_ERROR,
|
|
"%a: Fail to allocate get the device path for Controller %d.\n",
|
|
__FUNCTION__,
|
|
Controller
|
|
));
|
|
return Status;
|
|
}
|
|
|
|
Status = NvmeInitPrivateData (MmioBase, DevicePath, DevicePathLength);
|
|
if (EFI_ERROR (Status)) {
|
|
DEBUG ((
|
|
DEBUG_ERROR,
|
|
"%a: Controller initialization fail for Controller %d with Status - %r.\n",
|
|
__FUNCTION__,
|
|
Controller,
|
|
Status
|
|
));
|
|
} else {
|
|
DEBUG ((
|
|
DEBUG_INFO,
|
|
"%a: Controller %d has been successfully initialized.\n",
|
|
__FUNCTION__,
|
|
Controller
|
|
));
|
|
}
|
|
|
|
Controller++;
|
|
}
|
|
|
|
return EFI_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
Callback for EDKII_NVM_EXPRESS_HOST_CONTROLLER_PPI installation.
|
|
|
|
@param[in] PeiServices Pointer to PEI Services Table.
|
|
@param[in] NotifyDescriptor Pointer to the descriptor for the Notification
|
|
event that caused this function to execute.
|
|
@param[in] Ppi Pointer to the PPI data associated with this function.
|
|
|
|
@retval EFI_SUCCESS The function completes successfully
|
|
@retval Others Cannot initialize Nvme controller from given EDKII_NVM_EXPRESS_HOST_CONTROLLER_PPI
|
|
|
|
**/
|
|
EFI_STATUS
|
|
EFIAPI
|
|
NvmeHostControllerPpiInstallationCallback (
|
|
IN EFI_PEI_SERVICES **PeiServices,
|
|
IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
|
|
IN VOID *Ppi
|
|
)
|
|
{
|
|
EDKII_NVM_EXPRESS_HOST_CONTROLLER_PPI *NvmeHcPpi;
|
|
|
|
if (Ppi == NULL) {
|
|
return EFI_INVALID_PARAMETER;
|
|
}
|
|
|
|
NvmeHcPpi = (EDKII_NVM_EXPRESS_HOST_CONTROLLER_PPI *)Ppi;
|
|
|
|
return NvmeInitControllerFromHostControllerPpi (NvmeHcPpi);
|
|
}
|
|
|
|
/**
|
|
Entry point of the PEIM.
|
|
|
|
@param[in] FileHandle Handle of the file being invoked.
|
|
@param[in] PeiServices Describes the list of possible PEI Services.
|
|
|
|
@retval EFI_SUCCESS PPI successfully installed.
|
|
|
|
**/
|
|
EFI_STATUS
|
|
EFIAPI
|
|
NvmExpressPeimEntry (
|
|
IN EFI_PEI_FILE_HANDLE FileHandle,
|
|
IN CONST EFI_PEI_SERVICES **PeiServices
|
|
)
|
|
{
|
|
DEBUG ((DEBUG_INFO, "%a: Enters.\n", __FUNCTION__));
|
|
|
|
PeiServicesNotifyPpi (&mNvmeHostControllerNotify);
|
|
|
|
PeiServicesNotifyPpi (&mPciDevicePpiNotify);
|
|
|
|
return EFI_SUCCESS;
|
|
}
|