e1aaef001f
Add the SEC module for RISC-V Qemu virt machine support. It uses the PEI less design. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com> Acked-by: Jiewen Yao <Jiewen.yao@intel.com> Acked-by: Ard Biesheuvel <ardb@kernel.org>
22 lines
456 B
ArmAsm
22 lines
456 B
ArmAsm
/*
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Copyright (c) 2022 Ventana Micro Systems Inc.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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*/
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#include "SecMain.h"
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.text
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.align 3
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ASM_FUNC (_ModuleEntryPoint)
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/* Use Temp memory as the stack for calling to C code */
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li a4, FixedPcdGet32 (PcdOvmfSecPeiTempRamBase)
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li a5, FixedPcdGet32 (PcdOvmfSecPeiTempRamSize)
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/* Use Temp memory as the stack for calling to C code */
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add sp, a4, a5
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call SecStartup
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