0547ffbf6d
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4172 This patch moves the TDX APs nasm code from SecEntry.nasm to IntelTdxAPs.nasm. IntelTdxX64 and OvmfPkgX64 use the same nasm so that it can be easier to be managed. In the following patch there will be AcceptMemory related changes in IntelTdxAPs.nasm. Cc: Erdem Aktas <erdemaktas@google.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Min Xu <min.m.xu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
104 lines
3.3 KiB
NASM
104 lines
3.3 KiB
NASM
;------------------------------------------------------------------------------
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;*
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;* Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
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;* SPDX-License-Identifier: BSD-2-Clause-Patent
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;*
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;* CpuAsm.asm
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;*
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;* Abstract:
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;*
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;------------------------------------------------------------------------------
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#include <Base.h>
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DEFAULT REL
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SECTION .text
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extern ASM_PFX(SecCoreStartupWithStack)
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%macro tdcall 0
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db 0x66, 0x0f, 0x01, 0xcc
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%endmacro
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;
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; SecCore Entry Point
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;
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; Processor is in flat protected mode
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;
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; @param[in] RAX Initial value of the EAX register (BIST: Built-in Self Test)
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; @param[in] DI 'BP': boot-strap processor, or 'AP': application processor
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; @param[in] RBP Pointer to the start of the Boot Firmware Volume
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; @param[in] DS Selector allowing flat access to all addresses
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; @param[in] ES Selector allowing flat access to all addresses
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; @param[in] FS Selector allowing flat access to all addresses
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; @param[in] GS Selector allowing flat access to all addresses
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; @param[in] SS Selector allowing flat access to all addresses
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;
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; @return None This routine does not return
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;
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global ASM_PFX(_ModuleEntryPoint)
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ASM_PFX(_ModuleEntryPoint):
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;
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; Guest type is stored in OVMF_WORK_AREA
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;
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%define OVMF_WORK_AREA FixedPcdGet32 (PcdOvmfWorkAreaBase)
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%define VM_GUEST_TYPE_TDX 2
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mov eax, OVMF_WORK_AREA
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cmp byte[eax], VM_GUEST_TYPE_TDX
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jne InitStack
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%define TDCALL_TDINFO 1
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mov rax, TDCALL_TDINFO
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tdcall
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;
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; R8 [31:0] NUM_VCPUS
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; [63:32] MAX_VCPUS
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; R9 [31:0] VCPU_INDEX
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; Td Guest set the VCPU0 as the BSP, others are the APs
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; APs jump to spinloop and get released by DXE's MpInitLib
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;
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mov rax, r9
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and rax, 0xffff
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test rax, rax
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jz InitStack
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mov rsp, FixedPcdGet32 (PcdOvmfSecGhcbBackupBase)
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jmp ParkAp
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InitStack:
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;
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; Fill the temporary RAM with the initial stack value.
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; The loop below will seed the heap as well, but that's harmless.
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;
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mov rax, (FixedPcdGet32 (PcdInitValueInTempStack) << 32) | FixedPcdGet32 (PcdInitValueInTempStack)
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; qword to store
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mov rdi, FixedPcdGet32 (PcdOvmfSecPeiTempRamBase) ; base address,
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; relative to
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; ES
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mov rcx, FixedPcdGet32 (PcdOvmfSecPeiTempRamSize) / 8 ; qword count
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cld ; store from base
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; up
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rep stosq
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;
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; Load temporary RAM stack based on PCDs
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;
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%define SEC_TOP_OF_STACK (FixedPcdGet32 (PcdOvmfSecPeiTempRamBase) + \
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FixedPcdGet32 (PcdOvmfSecPeiTempRamSize))
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mov rsp, SEC_TOP_OF_STACK
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nop
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;
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; Setup parameters and call SecCoreStartupWithStack
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; rcx: BootFirmwareVolumePtr
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; rdx: TopOfCurrentStack
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;
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mov rcx, rbp
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mov rdx, rsp
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sub rsp, 0x20
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call ASM_PFX(SecCoreStartupWithStack)
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%include "../../IntelTdx/Sec/X64/IntelTdxAPs.nasm"
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