fe5da0927a
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3334 IntelFsp2WrapperPkg defines following PCDs: PcdCpuMicrocodePatchAddress PcdCpuMicrocodePatchRegionSize PcdFlashMicrocodeOffset But the PCD name caused confusion because UefiCpuPkg defines: PcdCpuMicrocodePatchAddress PcdCpuMicrocodePatchRegionSize PcdCpuMicrocodePatchAddress in IntelFsp2WrapperPkg means the base address of the FV that holds the microcode. PcdCpuMicrocodePatchAddress in UefiCpuPkg means the address of the microcode. The relationship between the PCDs is: IntelFsp2WrapperPkg.PcdCpuMicrocodePatchAddress + IntelFsp2WrapperPkg.PcdFlashMicrocodeOffset == UefiCpuPkg.PcdCpuMicrocodePatchAddress IntelFsp2WrapperPkg.PcdCpuMicrocodePatchRegionSize - IntelFsp2WrapperPkg.PcdFlashMicrocodeOffset == UefiCpuPkg.PcdCpuMicrocodePatchRegionSize To avoid confusion and actually the PCDs in IntelFsp2WrapperPkg are only used by a sample FSP-T wrapper, this patch removes the 3 PCDs defined in IntelFsp2WrapperPkg. The FSP-T wrapper is updated to directly use the ones in UefiCpuPkg. Signed-off-by: Jason Lou <yun.lou@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ray Ni <ray.ni@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
62 lines
1.6 KiB
C
62 lines
1.6 KiB
C
/** @file
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Sample to provide TempRamInitParams data.
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Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Library/PcdLib.h>
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#include <FspEas.h>
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typedef struct {
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UINT32 MicrocodeRegionBase;
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UINT32 MicrocodeRegionSize;
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UINT32 CodeRegionBase;
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UINT32 CodeRegionSize;
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} FSPT_CORE_UPD;
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typedef struct {
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FSP_UPD_HEADER FspUpdHeader;
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//
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// If platform does not support FSP spec 2.2 remove FSPT_ARCH_UPD structure.
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//
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FSPT_ARCH_UPD FsptArchUpd;
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FSPT_CORE_UPD FsptCoreUpd;
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} FSPT_UPD_CORE_DATA;
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GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD_CORE_DATA FsptUpdDataPtr = {
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{
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0x4450555F54505346,
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//
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// UPD header revision must be equal or greater than 2 when the structure is compliant with FSP spec 2.2.
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//
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0x02,
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{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
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}
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},
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//
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// If platform does not support FSP spec 2.2 remove FSPT_ARCH_UPD structure.
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//
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{
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0x01,
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{
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0x00, 0x00, 0x00
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},
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0x00000020,
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0x00000000,
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{
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
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}
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},
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{
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FixedPcdGet32 (PcdCpuMicrocodePatchAddress),
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FixedPcdGet32 (PcdCpuMicrocodePatchRegionSize),
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FixedPcdGet32 (PcdFlashCodeCacheAddress),
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FixedPcdGet32 (PcdFlashCodeCacheSize),
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}
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};
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