3cbfba02fe
https://svn.code.sf.net/p/edk2/code/trunk/edk2/, which are for MinnowBoard MAX open source project. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: David Wei <david.wei@intel.com> Reviewed-by: Mike Wu <mike.wu@intel.com> Reviewed-by: Hot Tian <hot.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16599 6f19259b-4bc3-4df7-8a09-765794883524
106 lines
3.2 KiB
Plaintext
106 lines
3.2 KiB
Plaintext
/**************************************************************************;
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;* *;
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;* *;
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;* Intel Corporation - ACPI Reference Code for the Baytrail *;
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;* Family of Customer Reference Boards. *;
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;* *;
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;* *;
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;* Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved *;
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;
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; This program and the accompanying materials are licensed and made available under
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; the terms and conditions of the BSD License that accompanies this distribution.
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; The full text of the license may be found at
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; http://opensource.org/licenses/bsd-license.php.
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;
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; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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;
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;* *;
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;* *;
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;**************************************************************************/
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// General Purpose Events. This Scope handles the Run-time and
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// Wake-time SCIs. The specific method called will be determined by
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// the _Lxx value, where xx equals the bit location in the General
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// Purpose Event register(s).
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Scope(\_GPE)
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{
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//
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// Software GPE caused the event.
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//
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Method(_L02)
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{
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// Clear GPE status bit.
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Store(0,GPEC)
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//
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// Handle DTS Thermal Events.
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//
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External(DTSE, IntObj)
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If(CondRefOf(DTSE))
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{
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If(LGreaterEqual(DTSE, 0x01))
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{
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Notify(\_TZ.TZ01,0x80)
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}
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}
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}
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//
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// PUNIT SCI event.
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//
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Method(_L04)
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{
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// Clear the PUNIT Status Bit.
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Store(1, PSCI)
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}
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//
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// IGD OpRegion SCI event (see IGD OpRegion/Software SCI BIOS SPEC).
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//
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Method(_L05)
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{
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If(LAnd(\_SB.PCI0.GFX0.GSSE, LNot(GSMI))) // Graphics software SCI event?
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{
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\_SB.PCI0.GFX0.GSCI() // Handle the SWSCI
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}
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}
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//
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// This PME event (PCH's GPE #13) is received when any PCH internal device with PCI Power Management capabilities
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// on bus 0 asserts the equivalent of the PME# signal.
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//
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Method(_L0D, 0)
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{
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If(LAnd(\_SB.PCI0.EHC1.PMEE, \_SB.PCI0.EHC1.PMES))
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{
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If(LNotEqual(OSEL, 1))
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{
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Store(1, \_SB.PCI0.EHC1.PMES) //Clear PME status
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Store(0, \_SB.PCI0.EHC1.PMEE) //Disable PME
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}
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Notify(\_SB.PCI0.EHC1, 0x02)
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}
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If(LAnd(\_SB.PCI0.XHC1.PMEE, \_SB.PCI0.XHC1.PMES))
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{
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If(LNotEqual(OSEL, 1))
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{
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Store(1, \_SB.PCI0.XHC1.PMES) //Clear PME status
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Store(0, \_SB.PCI0.XHC1.PMEE) //Disable PME
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}
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Notify(\_SB.PCI0.XHC1, 0x02)
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}
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If(LAnd(\_SB.PCI0.HDEF.PMEE, \_SB.PCI0.HDEF.PMES))
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{
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If(LNotEqual(OSEL, 1))
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{
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Store(1, \_SB.PCI0.HDEF.PMES) //Clear PME status
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Store(0, \_SB.PCI0.HDEF.PMEE) //Disable PME
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}
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Notify(\_SB.PCI0.HDEF, 0x02)
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}
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}
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}
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