3cbfba02fe
https://svn.code.sf.net/p/edk2/code/trunk/edk2/, which are for MinnowBoard MAX open source project. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: David Wei <david.wei@intel.com> Reviewed-by: Mike Wu <mike.wu@intel.com> Reviewed-by: Hot Tian <hot.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16599 6f19259b-4bc3-4df7-8a09-765794883524
267 lines
12 KiB
Plaintext
267 lines
12 KiB
Plaintext
/*-----------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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Intel Silvermont Processor Power Management BIOS Reference Code
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Copyright (c) 2006 - 2014, Intel Corporation
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This program and the accompanying materials are licensed and made available under
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the terms and conditions of the BSD License that accompanies this distribution.
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The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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Filename: CPU0IST.ASL
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Revision: Refer to Readme
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Date: Refer to Readme
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--------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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This Processor Power Management BIOS Source Code is furnished under license
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and may only be used or copied in accordance with the terms of the license.
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The information in this document is furnished for informational use only, is
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subject to change without notice, and should not be construed as a commitment
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by Intel Corporation. Intel Corporation assumes no responsibility or liability
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for any errors or inaccuracies that may appear in this document or any
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software that may be provided in association with this document.
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Except as permitted by such license, no part of this document may be
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reproduced, stored in a retrieval system, or transmitted in any form or by
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any means without the express written consent of Intel Corporation.
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WARNING: You are authorized and licensed to install and use this BIOS code
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ONLY on an IST PC. This utility may damage any system that does not
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meet these requirements.
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An IST PC is a computer which
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(1) Is capable of seamlessly and automatically transitioning among
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multiple performance states (potentially operating at different
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efficiency ratings) based upon power source changes, END user
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preference, processor performance demand, and thermal conditions; and
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(2) Includes an Intel Pentium II processors, Intel Pentium III
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processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4
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Processor-M, Intel Pentium M Processor, or any other future Intel
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processors that incorporates the capability to transition between
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different performance states by altering some, or any combination of,
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the following processor attributes: core voltage, core frequency, bus
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frequency, number of processor cores available, or any other attribute
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that changes the efficiency (instructions/unit time-power) at which the
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processor operates.
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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NOTES:
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(1) <TODO> - IF the trap range and port definitions do not match those
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specified by this reference code, this file must be modified IAW the
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individual implmentation.
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--------------------------------------------------------------------------------
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------------------------------------------------------------------------------*/
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DefinitionBlock (
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"CPU0IST.aml",
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"SSDT",
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0x01,
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"PmRef",
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"Cpu0Ist",
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0x3000
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)
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{
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External (\_PR.CPU0, DeviceObj)
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External (PDC0)
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External (CFGD)
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Scope(\_PR.CPU0)
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{
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//OperationRegion (DEB0, SystemIO, 0x80, 1) //DBG
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//Field (DEB0, ByteAcc,NoLock,Preserve) //DBG
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//{ DBG8, 8,} //DBG
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Name(_PPC, 0) // Initialize as All States Available.
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// NOTE: For CMP systems; this table is not loaded unless
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// the required driver support is present.
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// So, we do not check for those cases here.
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//
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// CFGD[0] = GV3 Capable/Enabled
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// PDCx[0] = OS Capable of Hardware P-State control
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//
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Method(_PCT,0)
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{
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If(LAnd(And(CFGD,0x0001), And(PDC0,0x0001)))
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{
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//Store(0xA0,DBG8) //DBG
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Return(Package() // Native Mode
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{
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ResourceTemplate(){Register(FfixedHW, 0, 0, 0)},
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ResourceTemplate(){Register(FfixedHW, 0, 0, 0)}
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})
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}
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// @NOTE: IO Trap is not supported. Therefore should not expose any IO interface for _PCT
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// For all other cases, report control through the
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// SMI interface. (The port used for SMM control is fixed up
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// by the initialization code.)
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//
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Return(Package() // SMM Mode
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{
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ResourceTemplate(){Register(FfixedHW, 0, 0, 0)},
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ResourceTemplate(){Register(FfixedHW, 0, 0, 0)}
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})
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}
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// NOTE: For CMP systems; this table is not loaded if MP
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// driver support is not present or P-State are disabled.
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//
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Method(_PSS,0)
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{
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//
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// Report NSPP if:
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// (1) GV3 capable (Not checked, see above.)
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// (2) Driver support direct hardware control
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// (3) MP driver support present (Not checked, see above.)
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// else;
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// Report SPSS
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//
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// PDCx[0] = OS Capable of Hardware P-State control
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//
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If(And(PDC0,0x0001)){
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//Store(0xB0,DBG8) //DBG
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Return(NPSS)
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}
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//Store(0xBF,DBG8) //DBG
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// Otherwise, report SMM mode
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//
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Return(SPSS)
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}
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Name(SPSS,Package()
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{
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Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
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Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
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Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
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Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
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Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
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Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
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Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
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Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
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Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
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Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
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Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
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Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
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Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
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Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
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Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
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Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}
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})
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Name(NPSS,Package()
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{
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Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
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Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
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Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
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Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
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Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
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Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
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Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
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Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
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Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
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Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
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Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
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Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
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Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
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Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
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Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
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Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}
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})
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// The _PSD object provides information to the OSPM related
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// to P-State coordination between processors in a multi-processor
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// configurations.
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//
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Method(_PSD,0)
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{
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//
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// IF CMP is supported/enabled
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// IF quad core processor
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// IF PDC[11]
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// Report 4 processors and HW_ALL as the coordination type
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// ELSE
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// Report 4 processors and SW_ALL as the coordination type
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// ELSE
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// IF PDC[11]
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// Report 2 processors and HW_ALL as the coordination type
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// ELSE
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// Report 2 processors and SW_ALL as the coordination type
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// ELSE
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// Report 1 processor and SW_ALL as the coordination type
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// (Domain 0)
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//
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// CFGD[24] = Two or more cores enabled
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// CFGD[23] = Four cores enabled
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// PDCx[11] = Hardware coordination with hardware feedback
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//
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If(And(CFGD,0x1000000)) // CMP Enabled.
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{
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If(And(CFGD,0x800000)) // 2 or 4 process.
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{
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If(And(PDC0,0x0800))
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{
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Return(Package(){ // HW_ALL
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Package(){
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5, // # entries.
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0, // Revision.
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0, // Domain #.
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0xFE, // Coord Type- HW_ALL.
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4 // # processors.
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}
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})
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} // If(And(PDC0,0x0800))
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Return(Package(){ // SW_ALL
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Package(){
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5, // # entries.
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0, // Revision.
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0, // Domain #.
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0xFC, // Coord Type- SW_ALL.
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4 // # processors.
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}
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})
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} else {
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Return(Package(){ // HW_ALL
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Package(){
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5, // # entries.
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0, // Revision.
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0, // Domain #.
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0xFE, // Coord Type- HW_ALL.
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2 // # processors.
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}
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})
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}
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} // If(And(CFGD,0x1000000)) // CMP Enabled.
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Return(Package(){ // SW_ALL
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Package(){
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5, // # entries.
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0, // Revision.
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0, // Domain #.
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0xFC, // Coord Type- SW_ALL.
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1 // # processors.
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}
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})
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} // Method(_PSD,0)
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} // Scope(\_PR.CPU0)
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} // End of Definition Block
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