f4dfad05dd
https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
58 lines
2.0 KiB
C
58 lines
2.0 KiB
C
/** @file
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*
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* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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**/
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#include "PrePeiCore.h"
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VOID
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EFIAPI
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SecondaryMain (
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IN UINTN MpId
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)
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{
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ASSERT(FALSE);
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}
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VOID
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EFIAPI
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PrimaryMain (
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IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint
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)
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{
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EFI_SEC_PEI_HAND_OFF SecCoreData;
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UINTN PpiListSize;
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EFI_PEI_PPI_DESCRIPTOR *PpiList;
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UINTN TemporaryRamBase;
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UINTN TemporaryRamSize;
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CreatePpiList (&PpiListSize, &PpiList);
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// Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at
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// the base of the primary core stack
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PpiListSize = ALIGN_VALUE(PpiListSize, CPU_STACK_ALIGNMENT);
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TemporaryRamBase = (UINTN)PcdGet64 (PcdCPUCoresStackBase) + PpiListSize;
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TemporaryRamSize = (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) - PpiListSize;
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//
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// Bind this information into the SEC hand-off state
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// Note: this must be in sync with the stuff in the asm file
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// Note also: HOBs (pei temp ram) MUST be above stack
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//
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SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF);
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SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet64 (PcdFvBaseAddress);
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SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdFvSize);
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SecCoreData.TemporaryRamBase = (VOID *)TemporaryRamBase; // We run on the primary core (and so we use the first stack)
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SecCoreData.TemporaryRamSize = TemporaryRamSize;
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SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase;
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SecCoreData.PeiTemporaryRamSize = ALIGN_VALUE (SecCoreData.TemporaryRamSize / 2, CPU_STACK_ALIGNMENT);
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SecCoreData.StackBase = (VOID *)((UINTN)SecCoreData.TemporaryRamBase + SecCoreData.PeiTemporaryRamSize);
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SecCoreData.StackSize = (TemporaryRamBase + TemporaryRamSize) - (UINTN)SecCoreData.StackBase;
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// Jump to PEI core entry point
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(PeiCoreEntryPoint)(&SecCoreData, PpiList);
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}
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