From 2ab49f46b9dbc340fa1d1261efa446e906e4fdc8 Mon Sep 17 00:00:00 2001
From: Jeremy Soller <jeremy@system76.com>
Date: Sun, 23 Feb 2020 12:51:37 -0700
Subject: [PATCH] Add power_on_s5 for DEEP_SX

---
 src/board/system76/lemp9/power.c | 28 +++++++++++++++++++++++++++-
 1 file changed, 27 insertions(+), 1 deletion(-)

diff --git a/src/board/system76/lemp9/power.c b/src/board/system76/lemp9/power.c
index daeb04b..9ca2950 100644
--- a/src/board/system76/lemp9/power.c
+++ b/src/board/system76/lemp9/power.c
@@ -87,8 +87,34 @@ void power_on_s5() {
 
 #if DEEP_SX
     // See Figure 12-18 in Whiskey Lake Platform Design Guide
+    // TODO - signal timing graph
+    // See Figure 12-24 in Whiskey Lake Platform Design Guide
+    // TODO - rail timing graph
+    
+    // TODO: Must have SL_SUS# set high by PCH
+    
+    // Enable VCCPRIM_* planes - must be enabled prior to USB power in order to
+    // avoid leakage
+    gpio_set(&VA_EC_EN, true);
+    tPCH06;
 
-    // TODO
+    // Enable VDD5
+    gpio_set(&DD_ON, true);
+
+    //TODO: Should SUS_ACK# be de-asserted here?
+    tPCH03;
+
+    // De-assert RSMRST#
+    gpio_set(&EC_RSMRST_N, true);
+
+    // Wait for PCH stability
+    tPCH18;
+
+    // Allow processor to control SUSB# and SUSC#
+    gpio_set(&EC_EN, true);
+
+    // Extra wait - TODO remove
+    delay_ms(200);
 #else // DEEP_SX
     // See Figure 12-19 in Whiskey Lake Platform Design Guide
     // TODO - signal timing graph