diff --git a/src/board/system76/darp5/peci.c b/src/board/system76/darp5/peci.c index 8dbc443..c7991b1 100644 --- a/src/board/system76/darp5/peci.c +++ b/src/board/system76/darp5/peci.c @@ -1,6 +1,7 @@ #include #include +#include #include #include #include @@ -77,40 +78,49 @@ void peci_init(void) { // PECI information can be found here: https://www.intel.com/content/dam/www/public/us/en/documents/design-guides/core-i7-lga-2011-guide.pdf void peci_event(void) { - // Wait for completion - while (HOSTAR & 1) {} - // Clear status - HOSTAR = HOSTAR; + if (power_state == POWER_STATE_S0) { + // Use PECI if in S0 state - // Enable PECI, clearing data fifo's - HOCTLR = (1 << 5) | (1 << 3); - // Set address to default - HOTRADDR = 0x30; - // Set write length - HOWRLR = 1; - // Set read length - HORDLR = 2; - // Set command - HOCMDR = 1; - // Start transaction - HOCTLR |= 1; + // Wait for completion + while (HOSTAR & 1) {} + // Clear status + HOSTAR = HOSTAR; - // Wait for completion - while (HOSTAR & 1) {} + // Enable PECI, clearing data fifo's + HOCTLR = (1 << 5) | (1 << 3); + // Set address to default + HOTRADDR = 0x30; + // Set write length + HOWRLR = 1; + // Set read length + HORDLR = 2; + // Set command + HOCMDR = 1; + // Start transaction + HOCTLR |= 1; - if (HOSTAR & (1 << 1)) { - // Use result if finished successfully - uint8_t low = HORDDR; - uint8_t high = HORDDR; - peci_offset = ((int16_t)high << 8) | (int16_t)low; + // Wait for completion + while (HOSTAR & 1) {} - peci_temp = PECI_TEMP(T_JUNCTION) + peci_offset; - peci_duty = fan_duty(peci_temp); + if (HOSTAR & (1 << 1)) { + // Use result if finished successfully + uint8_t low = HORDDR; + uint8_t high = HORDDR; + peci_offset = ((int16_t)high << 8) | (int16_t)low; + + peci_temp = PECI_TEMP(T_JUNCTION) + peci_offset; + peci_duty = fan_duty(peci_temp); + } else { + // Default to 50% if there is an error + peci_offset = 0; + peci_temp = 0; + peci_duty = PWM_DUTY(50); + } } else { - // Default to 50% if there is an error + // Turn fan off if not in S0 state peci_offset = 0; peci_temp = 0; - peci_duty = PWM_DUTY(50); + peci_duty = PWM_DUTY(0); } if (peci_duty != DCR2) { diff --git a/src/board/system76/darp5/power.c b/src/board/system76/darp5/power.c index 38b1b29..121a0d9 100644 --- a/src/board/system76/darp5/power.c +++ b/src/board/system76/darp5/power.c @@ -372,7 +372,7 @@ void power_event(void) { rst_last = rst_new; #if LEVEL >= LEVEL_DEBUG - static bool sus_last = false; + static bool sus_last = true; bool sus_new = gpio_get(&SLP_SUS_N); if (!sus_new && sus_last) { DEBUG("%02X: SLP_SUS# asserted\n", main_cycle); diff --git a/src/board/system76/galp3-c/peci.c b/src/board/system76/galp3-c/peci.c index 8dbc443..c7991b1 100644 --- a/src/board/system76/galp3-c/peci.c +++ b/src/board/system76/galp3-c/peci.c @@ -1,6 +1,7 @@ #include #include +#include #include #include #include @@ -77,40 +78,49 @@ void peci_init(void) { // PECI information can be found here: https://www.intel.com/content/dam/www/public/us/en/documents/design-guides/core-i7-lga-2011-guide.pdf void peci_event(void) { - // Wait for completion - while (HOSTAR & 1) {} - // Clear status - HOSTAR = HOSTAR; + if (power_state == POWER_STATE_S0) { + // Use PECI if in S0 state - // Enable PECI, clearing data fifo's - HOCTLR = (1 << 5) | (1 << 3); - // Set address to default - HOTRADDR = 0x30; - // Set write length - HOWRLR = 1; - // Set read length - HORDLR = 2; - // Set command - HOCMDR = 1; - // Start transaction - HOCTLR |= 1; + // Wait for completion + while (HOSTAR & 1) {} + // Clear status + HOSTAR = HOSTAR; - // Wait for completion - while (HOSTAR & 1) {} + // Enable PECI, clearing data fifo's + HOCTLR = (1 << 5) | (1 << 3); + // Set address to default + HOTRADDR = 0x30; + // Set write length + HOWRLR = 1; + // Set read length + HORDLR = 2; + // Set command + HOCMDR = 1; + // Start transaction + HOCTLR |= 1; - if (HOSTAR & (1 << 1)) { - // Use result if finished successfully - uint8_t low = HORDDR; - uint8_t high = HORDDR; - peci_offset = ((int16_t)high << 8) | (int16_t)low; + // Wait for completion + while (HOSTAR & 1) {} - peci_temp = PECI_TEMP(T_JUNCTION) + peci_offset; - peci_duty = fan_duty(peci_temp); + if (HOSTAR & (1 << 1)) { + // Use result if finished successfully + uint8_t low = HORDDR; + uint8_t high = HORDDR; + peci_offset = ((int16_t)high << 8) | (int16_t)low; + + peci_temp = PECI_TEMP(T_JUNCTION) + peci_offset; + peci_duty = fan_duty(peci_temp); + } else { + // Default to 50% if there is an error + peci_offset = 0; + peci_temp = 0; + peci_duty = PWM_DUTY(50); + } } else { - // Default to 50% if there is an error + // Turn fan off if not in S0 state peci_offset = 0; peci_temp = 0; - peci_duty = PWM_DUTY(50); + peci_duty = PWM_DUTY(0); } if (peci_duty != DCR2) { diff --git a/src/board/system76/galp3-c/power.c b/src/board/system76/galp3-c/power.c index 0af724a..0f9db81 100644 --- a/src/board/system76/galp3-c/power.c +++ b/src/board/system76/galp3-c/power.c @@ -369,7 +369,7 @@ void power_event(void) { rst_last = rst_new; #if LEVEL >= LEVEL_DEBUG - static bool sus_last = false; + static bool sus_last = true; bool sus_new = gpio_get(&SLP_SUS_N); if (!sus_new && sus_last) { DEBUG("%02X: SLP_SUS# asserted\n", main_cycle); diff --git a/src/board/system76/lemp9/peci.c b/src/board/system76/lemp9/peci.c index 8dbc443..c7991b1 100644 --- a/src/board/system76/lemp9/peci.c +++ b/src/board/system76/lemp9/peci.c @@ -1,6 +1,7 @@ #include #include +#include #include #include #include @@ -77,40 +78,49 @@ void peci_init(void) { // PECI information can be found here: https://www.intel.com/content/dam/www/public/us/en/documents/design-guides/core-i7-lga-2011-guide.pdf void peci_event(void) { - // Wait for completion - while (HOSTAR & 1) {} - // Clear status - HOSTAR = HOSTAR; + if (power_state == POWER_STATE_S0) { + // Use PECI if in S0 state - // Enable PECI, clearing data fifo's - HOCTLR = (1 << 5) | (1 << 3); - // Set address to default - HOTRADDR = 0x30; - // Set write length - HOWRLR = 1; - // Set read length - HORDLR = 2; - // Set command - HOCMDR = 1; - // Start transaction - HOCTLR |= 1; + // Wait for completion + while (HOSTAR & 1) {} + // Clear status + HOSTAR = HOSTAR; - // Wait for completion - while (HOSTAR & 1) {} + // Enable PECI, clearing data fifo's + HOCTLR = (1 << 5) | (1 << 3); + // Set address to default + HOTRADDR = 0x30; + // Set write length + HOWRLR = 1; + // Set read length + HORDLR = 2; + // Set command + HOCMDR = 1; + // Start transaction + HOCTLR |= 1; - if (HOSTAR & (1 << 1)) { - // Use result if finished successfully - uint8_t low = HORDDR; - uint8_t high = HORDDR; - peci_offset = ((int16_t)high << 8) | (int16_t)low; + // Wait for completion + while (HOSTAR & 1) {} - peci_temp = PECI_TEMP(T_JUNCTION) + peci_offset; - peci_duty = fan_duty(peci_temp); + if (HOSTAR & (1 << 1)) { + // Use result if finished successfully + uint8_t low = HORDDR; + uint8_t high = HORDDR; + peci_offset = ((int16_t)high << 8) | (int16_t)low; + + peci_temp = PECI_TEMP(T_JUNCTION) + peci_offset; + peci_duty = fan_duty(peci_temp); + } else { + // Default to 50% if there is an error + peci_offset = 0; + peci_temp = 0; + peci_duty = PWM_DUTY(50); + } } else { - // Default to 50% if there is an error + // Turn fan off if not in S0 state peci_offset = 0; peci_temp = 0; - peci_duty = PWM_DUTY(50); + peci_duty = PWM_DUTY(0); } if (peci_duty != DCR2) { diff --git a/src/board/system76/lemp9/power.c b/src/board/system76/lemp9/power.c index 0af724a..0f9db81 100644 --- a/src/board/system76/lemp9/power.c +++ b/src/board/system76/lemp9/power.c @@ -369,7 +369,7 @@ void power_event(void) { rst_last = rst_new; #if LEVEL >= LEVEL_DEBUG - static bool sus_last = false; + static bool sus_last = true; bool sus_new = gpio_get(&SLP_SUS_N); if (!sus_new && sus_last) { DEBUG("%02X: SLP_SUS# asserted\n", main_cycle);