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Add IT5570E support with correct I2C channel

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This commit is contained in:
Jeremy Soller
2020-01-10 08:07:18 -07:00
parent 26d01841d1
commit 89e3f3894f
21 changed files with 874 additions and 25 deletions
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50
src/ec/it8587e/i2c.c
View File

@ -6,30 +6,36 @@
//TODO: find best value
#define I2C_TIMEOUT 10000
#define HOSTA HOSTAA
#define HOCTL HOCTLA
#define HOCTL2 HOCTL2A
#define HOBDB HOBDBA
#define TRASLA TRASLAA
void i2c_reset(bool kill) {
if (HOSTAA & HOSTA_BUSY) {
if (HOSTA & HOSTA_BUSY) {
// Set kill bit
if (kill) HOCTLA |= (1 << 1);
if (kill) HOCTL |= (1 << 1);
// Wait for host to finish
while (HOSTAA & HOSTA_BUSY) {}
while (HOSTA & HOSTA_BUSY) {}
}
// Clear status register
HOSTAA = HOSTAA;
HOSTA = HOSTA;
// Clear current command
HOCTLA = 0;
HOCTL = 0;
// Disable host interface
HOCTL2A = 0;
HOCTL2 = 0;
}
int i2c_start(uint8_t addr, bool read) {
// If we are already in a transaction
if (HOSTAA & HOSTA_BYTE_DONE) {
if (HOSTA & HOSTA_BYTE_DONE) {
// If we are switching direction
if ((TRASLAA & 1) != read) {
if ((TRASLA & 1) != read) {
// If we are switching to read mode
if (read) {
// Enable direction switch
HOCTL2A |= (1 << 3) | (1 << 2);
HOCTL2 |= (1 << 3) | (1 << 2);
} else {
// Unsupported!
i2c_reset(true);
@ -40,10 +46,10 @@ int i2c_start(uint8_t addr, bool read) {
i2c_reset(true);
// Enable host controller with i2c compatibility
HOCTL2A = (1 << 1) | 1;
HOCTL2 = (1 << 1) | 1;
// Set address
TRASLAA = (addr << 1) | read;
TRASLA = (addr << 1) | read;
}
return 0;
@ -51,9 +57,9 @@ int i2c_start(uint8_t addr, bool read) {
void i2c_stop(void) {
// Disable i2c compatibility
HOCTL2A &= ~(1 << 1);
HOCTL2 &= ~(1 << 1);
// Clear status
HOSTAA = HOSTAA;
HOSTA = HOSTA;
i2c_reset(false);
}
@ -65,33 +71,33 @@ static int i2c_transaction(uint8_t * data, int length, bool read) {
// If last byte
if ((i + 1) == length) {
// Set last byte bit
HOCTLA |= (1 << 5);
HOCTL |= (1 << 5);
}
} else {
// Write byte
HOBDBA = data[i];
HOBDB = data[i];
}
// If we are already in a transaction
if (HOSTAA & HOSTA_BYTE_DONE) {
if (HOSTA & HOSTA_BYTE_DONE) {
// Clear status to process next byte
HOSTAA = HOSTAA;
HOSTA = HOSTA;
} else {
// Start new transaction
HOCTLA = (1 << 6) | (0b111 << 2);
HOCTL = (1 << 6) | (0b111 << 2);
}
// If we are waiting on direction switch
if (HOCTL2A & (1 << 2)) {
if (HOCTL2 & (1 << 2)) {
// Complete direction switch
HOCTL2A &= ~(1 << 2);
HOCTL2 &= ~(1 << 2);
}
// Wait for byte done, timeout, or error
uint8_t status;
uint32_t timeout = I2C_TIMEOUT;
for(timeout = I2C_TIMEOUT; timeout > 0; timeout--) {
status = HOSTAA;
status = HOSTA;
// If error occured, kill transaction and return error
if (status & HOSTA_ERR) {
i2c_reset(true);
@ -110,7 +116,7 @@ static int i2c_transaction(uint8_t * data, int length, bool read) {
if (read) {
// Read byte
data[i] = HOBDBA;
data[i] = HOBDB;
}
}

4
src/ec/it8587e/include/ec/smbus.h
View File

@ -31,8 +31,6 @@ volatile uint8_t __xdata __at(0x1C06) HOBDBA;
volatile uint8_t __xdata __at(0x1C07) PECERCA;
// Receive slave address for channel A
volatile uint8_t __xdata __at(0x1C08) RESLADRA;
// Receive slave address 2 for channel A
volatile uint8_t __xdata __at(0x1C3F) RESLADR2A;
// Slave data for channel A
volatile uint8_t __xdata __at(0x1C09) SLDAA;
// SMBus pin control for channel A
@ -49,6 +47,8 @@ volatile uint8_t __xdata __at(0x1C0E) NDLBA;
volatile uint8_t __xdata __at(0x1C0F) NDHBA;
// Host control 2 for channel A
volatile uint8_t __xdata __at(0x1C10) HOCTL2A;
// Receive slave address 2 for channel A
volatile uint8_t __xdata __at(0x1C3F) RESLADR2A;
// SMCLK timing setting for channel A
volatile uint8_t __xdata __at(0x1C40) SCLKTSA;