Cleanup use of scratch rom for SPI flashing, prepare to implement no-reset flashing process
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14bb3af80b
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a24f9ed3ae
@ -8,9 +8,10 @@ uint8_t __code __at(SCRATCH_OFFSET) scratch_rom[] = {
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#include <scratch.h>
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};
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volatile uint8_t __xdata __at(0x1040) SCAR0L;
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volatile uint8_t __xdata __at(0x1041) SCAR0M;
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volatile uint8_t __xdata __at(0x1042) SCAR0H;
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// SCAR1 is in xram at 0x800-0xC00
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volatile uint8_t __xdata __at(0x1043) SCAR1L;
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volatile uint8_t __xdata __at(0x1044) SCAR1M;
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volatile uint8_t __xdata __at(0x1045) SCAR1H;
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// Enter or exit scratch ROM
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void scratch_trampoline(void) {
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@ -18,10 +19,10 @@ void scratch_trampoline(void) {
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EA = 0;
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// Use DMA mapping to copy flash data
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SCAR0H = 0x80;
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SCAR0L = (uint8_t)(SCRATCH_OFFSET);
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SCAR0M = (uint8_t)(SCRATCH_OFFSET >> 8);
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SCAR0H = 0;
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SCAR1H = 0x80;
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SCAR1L = (uint8_t)(SCRATCH_OFFSET);
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SCAR1M = (uint8_t)(SCRATCH_OFFSET >> 8);
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SCAR1H = 0;
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// Jump to scratch reset function
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__asm__("ljmp " xstr(SCRATCH_OFFSET));
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@ -22,7 +22,10 @@ volatile uint8_t __xdata __at(0x105C) HRAMW1BA;
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volatile uint8_t __xdata __at(0x105D) HRAMW0AAS;
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// Host RAM window 1 access allow size
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volatile uint8_t __xdata __at(0x105E) HRAMW1AAS;
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// Flash control register 3
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volatile uint8_t __xdata __at(0x1063) FLHCTRL3;
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// EC indirect flash access
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volatile uint8_t __xdata __at(0x103B) ECINDAR0;
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volatile uint8_t __xdata __at(0x103C) ECINDAR1;
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volatile uint8_t __xdata __at(0x103D) ECINDAR2;
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@ -35,51 +38,8 @@ volatile uint8_t __xdata __at(0x1F07) EWDKEYR;
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static volatile uint8_t __xdata __at(0xE00) smfi_cmd[256];
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static volatile uint8_t __xdata __at(0xF00) smfi_dbg[256];
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void smfi_init(void) {
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int i;
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// Clear command region
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for (i = 1; i < ARRAY_SIZE(smfi_cmd); i++) {
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smfi_cmd[i] = 0x00;
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}
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// Clear host command last
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smfi_cmd[0] = 0x00;
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// Clear debug region
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for (i = 1; i < ARRAY_SIZE(smfi_dbg); i++) {
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smfi_dbg[i] = 0x00;
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}
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// Clear tail last
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smfi_dbg[0] = 0x00;
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// H2RAM window 0 address 0xE00 - 0xEFF, read/write
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HRAMW0BA = 0xE0;
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HRAMW0AAS = 0x04;
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// H2RAM window 1 address 0xF00 - 0xFFF, read/write
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HRAMW1BA = 0xF0;
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HRAMW1AAS = 0x04;
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// Enable H2RAM window 0 and 1 using LPC I/O
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HRAMWC |= 0x13;
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}
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static enum Result cmd_debug(void) {
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int i;
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for (i = 2; i < ARRAY_SIZE(smfi_cmd); i++) {
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uint8_t b = smfi_cmd[i];
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if (b == 0) break;
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putchar(b);
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}
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return RES_OK;
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}
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static enum Result cmd_spi(void) {
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static enum Result cmd_spi_scratch(void) __critical {
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uint8_t flags = smfi_cmd[2];
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#ifdef __SCRATCH__
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uint8_t len = smfi_cmd[3];
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// Enable chip
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@ -112,12 +72,61 @@ static enum Result cmd_spi(void) {
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}
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return RES_OK;
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}
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void smfi_init(void) {
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int i;
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// Clear command region
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for (i = 1; i < ARRAY_SIZE(smfi_cmd); i++) {
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smfi_cmd[i] = 0x00;
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}
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// Clear host command last
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smfi_cmd[0] = 0x00;
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// Clear debug region
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for (i = 1; i < ARRAY_SIZE(smfi_dbg); i++) {
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smfi_dbg[i] = 0x00;
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}
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// Clear tail last
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smfi_dbg[0] = 0x00;
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// H2RAM window 0 address 0xE00 - 0xEFF, read/write
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HRAMW0BA = 0xE0;
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HRAMW0AAS = 0x04;
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// H2RAM window 1 address 0xF00 - 0xFFF, read/write
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HRAMW1BA = 0xF0;
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HRAMW1AAS = 0x04;
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// Enable H2RAM window 0 and 1 using LPC I/O
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HRAMWC |= 0x13;
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// Enable backup ROM access
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FLHCTRL3 |= (1 << 3);
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}
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static enum Result cmd_debug(void) {
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int i;
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for (i = 2; i < ARRAY_SIZE(smfi_cmd); i++) {
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uint8_t b = smfi_cmd[i];
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if (b == 0) break;
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putchar(b);
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}
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return RES_OK;
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}
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static enum Result cmd_spi(void) {
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#ifdef __SCRATCH__
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return cmd_spi_scratch();
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#else
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if (flags & CMD_SPI_FLAG_SCRATCH) {
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if (smfi_cmd[2] & CMD_SPI_FLAG_SCRATCH) {
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scratch_trampoline();
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}
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// Cannot use SPI bus while running EC from SPI, or trampoline failed
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// Cannot use follow mode unless running from scratch rom
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return RES_ERR;
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#endif
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}
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@ -8,9 +8,10 @@ uint8_t __code __at(SCRATCH_OFFSET) scratch_rom[] = {
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#include <scratch.h>
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};
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volatile uint8_t __xdata __at(0x1040) SCAR0L;
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volatile uint8_t __xdata __at(0x1041) SCAR0M;
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volatile uint8_t __xdata __at(0x1042) SCAR0H;
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// SCAR1 is in xram at 0x800-0xC00
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volatile uint8_t __xdata __at(0x1043) SCAR1L;
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volatile uint8_t __xdata __at(0x1044) SCAR1M;
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volatile uint8_t __xdata __at(0x1045) SCAR1H;
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// Enter or exit scratch ROM
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void scratch_trampoline(void) {
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@ -18,10 +19,10 @@ void scratch_trampoline(void) {
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EA = 0;
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// Use DMA mapping to copy flash data
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SCAR0H = 0x80;
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SCAR0L = (uint8_t)(SCRATCH_OFFSET);
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SCAR0M = (uint8_t)(SCRATCH_OFFSET >> 8);
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SCAR0H = 0;
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SCAR1H = 0x80;
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SCAR1L = (uint8_t)(SCRATCH_OFFSET);
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SCAR1M = (uint8_t)(SCRATCH_OFFSET >> 8);
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SCAR1H = 0;
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// Jump to scratch reset function
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__asm__("ljmp " xstr(SCRATCH_OFFSET));
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@ -22,7 +22,10 @@ volatile uint8_t __xdata __at(0x105C) HRAMW1BA;
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volatile uint8_t __xdata __at(0x105D) HRAMW0AAS;
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// Host RAM window 1 access allow size
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volatile uint8_t __xdata __at(0x105E) HRAMW1AAS;
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// Flash control register 3
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volatile uint8_t __xdata __at(0x1063) FLHCTRL3;
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// EC indirect flash access
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volatile uint8_t __xdata __at(0x103B) ECINDAR0;
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volatile uint8_t __xdata __at(0x103C) ECINDAR1;
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volatile uint8_t __xdata __at(0x103D) ECINDAR2;
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@ -35,51 +38,8 @@ volatile uint8_t __xdata __at(0x1F07) EWDKEYR;
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static volatile uint8_t __xdata __at(0xE00) smfi_cmd[256];
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static volatile uint8_t __xdata __at(0xF00) smfi_dbg[256];
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void smfi_init(void) {
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int i;
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// Clear command region
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for (i = 1; i < ARRAY_SIZE(smfi_cmd); i++) {
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smfi_cmd[i] = 0x00;
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}
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// Clear host command last
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smfi_cmd[0] = 0x00;
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// Clear debug region
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for (i = 1; i < ARRAY_SIZE(smfi_dbg); i++) {
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smfi_dbg[i] = 0x00;
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}
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// Clear tail last
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smfi_dbg[0] = 0x00;
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// H2RAM window 0 address 0xE00 - 0xEFF, read/write
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HRAMW0BA = 0xE0;
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HRAMW0AAS = 0x04;
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// H2RAM window 1 address 0xF00 - 0xFFF, read/write
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HRAMW1BA = 0xF0;
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HRAMW1AAS = 0x04;
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// Enable H2RAM window 0 and 1 using LPC I/O
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HRAMWC |= 0x13;
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}
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static enum Result cmd_debug(void) {
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int i;
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for (i = 2; i < ARRAY_SIZE(smfi_cmd); i++) {
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uint8_t b = smfi_cmd[i];
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if (b == 0) break;
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putchar(b);
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}
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return RES_OK;
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}
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static enum Result cmd_spi(void) {
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static enum Result cmd_spi_scratch(void) __critical {
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uint8_t flags = smfi_cmd[2];
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#ifdef __SCRATCH__
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uint8_t len = smfi_cmd[3];
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// Enable chip
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@ -112,12 +72,61 @@ static enum Result cmd_spi(void) {
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}
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return RES_OK;
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}
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void smfi_init(void) {
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int i;
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// Clear command region
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for (i = 1; i < ARRAY_SIZE(smfi_cmd); i++) {
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smfi_cmd[i] = 0x00;
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}
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// Clear host command last
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smfi_cmd[0] = 0x00;
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// Clear debug region
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for (i = 1; i < ARRAY_SIZE(smfi_dbg); i++) {
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smfi_dbg[i] = 0x00;
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}
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// Clear tail last
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smfi_dbg[0] = 0x00;
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// H2RAM window 0 address 0xE00 - 0xEFF, read/write
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HRAMW0BA = 0xE0;
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HRAMW0AAS = 0x04;
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// H2RAM window 1 address 0xF00 - 0xFFF, read/write
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HRAMW1BA = 0xF0;
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HRAMW1AAS = 0x04;
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// Enable H2RAM window 0 and 1 using LPC I/O
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HRAMWC |= 0x13;
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// Enable backup ROM access
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FLHCTRL3 |= (1 << 3);
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}
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static enum Result cmd_debug(void) {
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int i;
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for (i = 2; i < ARRAY_SIZE(smfi_cmd); i++) {
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uint8_t b = smfi_cmd[i];
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if (b == 0) break;
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putchar(b);
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}
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return RES_OK;
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}
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static enum Result cmd_spi(void) {
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#ifdef __SCRATCH__
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return cmd_spi_scratch();
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#else
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if (flags & CMD_SPI_FLAG_SCRATCH) {
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if (smfi_cmd[2] & CMD_SPI_FLAG_SCRATCH) {
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scratch_trampoline();
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}
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// Cannot use SPI bus while running EC from SPI, or trampoline failed
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// Cannot use follow mode unless running from scratch rom
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return RES_ERR;
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#endif
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}
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@ -8,6 +8,7 @@ uint8_t __code __at(SCRATCH_OFFSET) scratch_rom[] = {
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#include <scratch.h>
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};
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// SCAR0 is stored in processor cache, not in xram
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volatile uint8_t __xdata __at(0x1040) SCAR0L;
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volatile uint8_t __xdata __at(0x1041) SCAR0M;
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volatile uint8_t __xdata __at(0x1042) SCAR0H;
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@ -22,7 +22,10 @@ volatile uint8_t __xdata __at(0x105C) HRAMW1BA;
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volatile uint8_t __xdata __at(0x105D) HRAMW0AAS;
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// Host RAM window 1 access allow size
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volatile uint8_t __xdata __at(0x105E) HRAMW1AAS;
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// Flash control register 3
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volatile uint8_t __xdata __at(0x1063) FLHCTRL3;
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// EC indirect flash access
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volatile uint8_t __xdata __at(0x103B) ECINDAR0;
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volatile uint8_t __xdata __at(0x103C) ECINDAR1;
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volatile uint8_t __xdata __at(0x103D) ECINDAR2;
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@ -35,51 +38,8 @@ volatile uint8_t __xdata __at(0x1F07) EWDKEYR;
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static volatile uint8_t __xdata __at(0xE00) smfi_cmd[256];
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static volatile uint8_t __xdata __at(0xF00) smfi_dbg[256];
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void smfi_init(void) {
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int i;
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// Clear command region
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for (i = 1; i < ARRAY_SIZE(smfi_cmd); i++) {
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smfi_cmd[i] = 0x00;
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}
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// Clear host command last
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smfi_cmd[0] = 0x00;
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// Clear debug region
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for (i = 1; i < ARRAY_SIZE(smfi_dbg); i++) {
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smfi_dbg[i] = 0x00;
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}
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// Clear tail last
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smfi_dbg[0] = 0x00;
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// H2RAM window 0 address 0xE00 - 0xEFF, read/write
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HRAMW0BA = 0xE0;
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HRAMW0AAS = 0x04;
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// H2RAM window 1 address 0xF00 - 0xFFF, read/write
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HRAMW1BA = 0xF0;
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HRAMW1AAS = 0x04;
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// Enable H2RAM window 0 and 1 using LPC I/O
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HRAMWC |= 0x13;
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}
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static enum Result cmd_debug(void) {
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int i;
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for (i = 2; i < ARRAY_SIZE(smfi_cmd); i++) {
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uint8_t b = smfi_cmd[i];
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if (b == 0) break;
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putchar(b);
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}
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return RES_OK;
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}
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static enum Result cmd_spi(void) {
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static enum Result cmd_spi_scratch(void) __critical {
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uint8_t flags = smfi_cmd[2];
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#ifdef __SCRATCH__
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uint8_t len = smfi_cmd[3];
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// Enable chip
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@ -112,12 +72,61 @@ static enum Result cmd_spi(void) {
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}
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return RES_OK;
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}
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void smfi_init(void) {
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int i;
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// Clear command region
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for (i = 1; i < ARRAY_SIZE(smfi_cmd); i++) {
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smfi_cmd[i] = 0x00;
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}
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// Clear host command last
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smfi_cmd[0] = 0x00;
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// Clear debug region
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for (i = 1; i < ARRAY_SIZE(smfi_dbg); i++) {
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smfi_dbg[i] = 0x00;
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}
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// Clear tail last
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smfi_dbg[0] = 0x00;
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// H2RAM window 0 address 0xE00 - 0xEFF, read/write
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HRAMW0BA = 0xE0;
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HRAMW0AAS = 0x04;
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// H2RAM window 1 address 0xF00 - 0xFFF, read/write
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HRAMW1BA = 0xF0;
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HRAMW1AAS = 0x04;
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// Enable H2RAM window 0 and 1 using LPC I/O
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HRAMWC |= 0x13;
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// Enable backup ROM access
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FLHCTRL3 |= (1 << 3);
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}
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static enum Result cmd_debug(void) {
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int i;
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for (i = 2; i < ARRAY_SIZE(smfi_cmd); i++) {
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uint8_t b = smfi_cmd[i];
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if (b == 0) break;
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putchar(b);
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}
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return RES_OK;
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}
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static enum Result cmd_spi(void) {
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#ifdef __SCRATCH__
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return cmd_spi_scratch();
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#else
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if (flags & CMD_SPI_FLAG_SCRATCH) {
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if (smfi_cmd[2] & CMD_SPI_FLAG_SCRATCH) {
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scratch_trampoline();
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}
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// Cannot use SPI bus while running EC from SPI, or trampoline failed
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// Cannot use follow mode unless running from scratch rom
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return RES_ERR;
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#endif
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}
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