diff --git a/src/arch/8051/arch.mk b/src/arch/8051/arch.mk
index 41616db..2553018 100644
--- a/src/arch/8051/arch.mk
+++ b/src/arch/8051/arch.mk
@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: GPL-3.0-only
 
-CC=sdcc -mmcs51 --model-large --xram-size $(SRAM_SIZE) --Werror
+CC=sdcc -mmcs51 --model-large --code-size $(CODE_SIZE) --xram-size $(SRAM_SIZE) --Werror
 OBJ=$(patsubst src/%.c,$(BUILD)/%.rel,$(SRC))
 
 # Run EC rom in simulator
@@ -14,7 +14,7 @@ sim: $(BUILD)/ec.rom
 # Convert from Intel Hex file to binary file
 $(BUILD)/ec.rom: $(BUILD)/ec.ihx
 	@mkdir -p $(@D)
-	makebin -p < $< > $@
+	makebin -s $(CODE_SIZE) -p < $< > $@
 
 # Link object files into Intel Hex file
 $(BUILD)/ec.ihx: $(OBJ)
diff --git a/src/ec/it5570e/ec.mk b/src/ec/it5570e/ec.mk
index 5067487..838806c 100644
--- a/src/ec/it5570e/ec.mk
+++ b/src/ec/it5570e/ec.mk
@@ -2,6 +2,9 @@
 
 ARCH=8051
 
+# 64 KB is the max without banking
+CODE_SIZE=65536
+
 # SRAM is 6144 bytes, only 4096 bytes are mapped at address 0. Region at
 # 0x0E00-0x1000 is used for AP communication. So this is brought down to 2048,
 # which matches it8587e limits
diff --git a/src/ec/it8587e/ec.mk b/src/ec/it8587e/ec.mk
index 1ce94c6..31e7162 100644
--- a/src/ec/it8587e/ec.mk
+++ b/src/ec/it8587e/ec.mk
@@ -2,5 +2,8 @@
 
 ARCH=8051
 
+# 64 KB is the max without banking
+CODE_SIZE=65536
+
 # SRAM is 4096 bytes, but SRAM at address 2048 is used for scratch ROM
 SRAM_SIZE=2048