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gaze18-3050: Fix GPIOs for power sequence

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Signed-off-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
Tim Crawford
2023-02-21 12:35:12 -07:00
committed by Jeremy Soller
parent 60f9cfc8d6
commit c7bc078cbd
2 changed files with 4 additions and 4 deletions
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5
src/board/system76/gaze18-3050/gpio.c
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@ -10,6 +10,7 @@ struct Gpio __code ALL_SYS_PWRGD = GPIO(C, 0);
struct Gpio __code BKL_EN = GPIO(C, 7);
struct Gpio __code BUF_PLT_RST_N = GPIO(D, 2); // renamed to ESPI_RESET_N
struct Gpio __code CCD_EN = GPIO(D, 1);
struct Gpio __code CPU_C10_GATE_N = GPIO(C, 6);
struct Gpio __code DD_ON = GPIO(E, 4);
struct Gpio __code DGPU_PWR_EN = GPIO(J, 2);
struct Gpio __code EC_EN = GPIO(B, 6); // renamed to SUSBC_EN#
@ -22,7 +23,7 @@ struct Gpio __code LED_BAT_FULL = GPIO(J, 0);
struct Gpio __code LED_PWR = GPIO(D, 0);
struct Gpio __code LID_SW_N = GPIO(B, 1);
struct Gpio __code PCH_DPWROK_EC = GPIO(H, 4);
//struct Gpio __code PM_PWROK = GPIO(C, 6);
struct Gpio __code PCH_PWROK_EC = GPIO(F, 3);
struct Gpio __code PWR_BTN_N = GPIO(D, 5);
struct Gpio __code PWR_SW_N = GPIO(B, 3);
struct Gpio __code SLP_SUS_N = GPIO(J, 4);
@ -44,8 +45,6 @@ void gpio_init() {
GCR8 = BIT(4);
// Enable LPC reset on GPD2
GCR = 0b10 << 1;
GCR1 = 0x00;
// Disable UARTs
GCR6 = 0;
// Enable SMBus channel 4

3
src/board/system76/gaze18-3050/include/board/gpio.h
View File

@ -14,6 +14,7 @@ extern struct Gpio __code BKL_EN;
#define HAVE_BT_EN 0
extern struct Gpio __code BUF_PLT_RST_N;
extern struct Gpio __code CCD_EN;
extern struct Gpio __code CPU_C10_GATE_N;
extern struct Gpio __code DD_ON;
extern struct Gpio __code DGPU_PWR_EN;
extern struct Gpio __code EC_EN;
@ -27,7 +28,7 @@ extern struct Gpio __code LED_BAT_FULL;
extern struct Gpio __code LED_PWR;
extern struct Gpio __code LID_SW_N;
extern struct Gpio __code PCH_DPWROK_EC;
#define HAVE_PCH_PWROK_EC 0
extern struct Gpio __code PCH_PWROK_EC;
#define HAVE_PM_PWROK 0
extern struct Gpio __code PWR_BTN_N;
extern struct Gpio __code PWR_SW_N;