350 lines
8.8 KiB
C
350 lines
8.8 KiB
C
// SPDX-License-Identifier: GPL-3.0-only
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#include <board/fan.h>
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#include <board/gpio.h>
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#include <board/peci.h>
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#include <board/power.h>
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#include <common/debug.h>
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#include <common/macro.h>
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#include <ec/espi.h>
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#include <ec/gpio.h>
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#include <ec/pwm.h>
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// Fan speed is the lowest requested over HEATUP seconds
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#ifndef BOARD_HEATUP
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#define BOARD_HEATUP 4
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#endif
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static uint8_t FAN_HEATUP[BOARD_HEATUP] = { 0 };
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// Fan speed is the highest HEATUP speed over COOLDOWN seconds
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#ifndef BOARD_COOLDOWN
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#define BOARD_COOLDOWN 10
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#endif
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static uint8_t FAN_COOLDOWN[BOARD_COOLDOWN] = { 0 };
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// Tjunction = 100C for i7-8565U (and probably the same for all WHL-U)
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#define T_JUNCTION 100
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bool peci_on = false;
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int16_t peci_temp = 0;
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#define PECI_TEMP(X) ((int16_t)(X))
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// clang-format off
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#define FAN_POINT(T, D) { .temp = PECI_TEMP(T), .duty = PWM_DUTY(D) }
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// clang-format on
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// Fan curve with temperature in degrees C, duty cycle in percent
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static struct FanPoint __code FAN_POINTS[] = {
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#ifdef BOARD_FAN_POINTS
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BOARD_FAN_POINTS
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#else
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FAN_POINT(70, 40),
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FAN_POINT(75, 50),
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FAN_POINT(80, 60),
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FAN_POINT(85, 65),
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FAN_POINT(90, 65)
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#endif
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};
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static struct Fan __code FAN = {
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.points = FAN_POINTS,
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.points_size = ARRAY_SIZE(FAN_POINTS),
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.heatup = FAN_HEATUP,
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.heatup_size = ARRAY_SIZE(FAN_HEATUP),
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.cooldown = FAN_COOLDOWN,
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.cooldown_size = ARRAY_SIZE(FAN_COOLDOWN),
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.interpolate = SMOOTH_FANS != 0,
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};
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#if CONFIG_BUS_ESPI
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void peci_init(void) {}
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// Returns true if peci is available
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bool peci_available(void) {
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// PECI is available if PLTRST_N is high
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// Do not wake CPU from C10 if HOST_C10 virtual wire is high
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//TODO: wake CPU every 8 seconds following Intel recommendation?
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return (vw_get(&VW_PLTRST_N) == VWS_HIGH) && (vw_get(&VW_HOST_C10) != VWS_HIGH);
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}
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// Returns true on success, false on error
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bool peci_get_temp(int16_t * data) {
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//TODO: Wait for completion?
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// Clear upstream status
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ESUCTRL0 = ESUCTRL0;
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// Clear OOB status
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ESOCTRL0 = ESOCTRL0;
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// Set upstream cycle type
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ESUCTRL1 = ESUCTRL1_OOB;
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// Set upstream tag / length[11:8]
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ESUCTRL2 = 0;
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// Set upstream length [7:0] (size of PECI data plus 3)
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ESUCTRL3 = 8;
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// Destination address (0x10 is PCH, left shifted by one)
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UDB[0] = 0x10 << 1;
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// Command code (0x01 is PECI)
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UDB[1] = 0x01;
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// Set byte count
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UDB[2] = 5;
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// Set source address (0x0F is EC, left shifted by one, or with 1)
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UDB[3] = (0x0F << 1) | 1;
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// PECI target address (0x30 is default)
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UDB[4] = 0x30;
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// PECI write length
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UDB[5] = 1;
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// PECI read length
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UDB[6] = 2;
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// PECI command (0x01 = GetTemp)
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UDB[7] = 0x01;
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// Set upstream enable
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ESUCTRL0 |= ESUCTRL0_ENABLE;
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// Set upstream go
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ESUCTRL0 |= ESUCTRL0_GO;
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// Wait until upstream done
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while (!(ESUCTRL0 & ESUCTRL0_DONE)) {}
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// Wait for response
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//TODO: do this asynchronously to avoid delays?
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while (!(ESOCTRL0 & ESOCTRL0_STATUS)) {}
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// Read response length
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uint8_t len = ESOCTRL4;
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if (len >= 7) {
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//TODO: verify packet type, handle PECI status
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// Received enough data for temperature
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uint8_t low = PUTOOBDB[5];
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uint8_t high = PUTOOBDB[6];
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*data = (((int16_t)high << 8) | (int16_t)low);
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return true;
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} else {
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// Did not receive enough data
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return false;
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}
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}
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// Returns positive completion code on success, negative completion code or
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// negative (0x1000 | status register) on PECI hardware error
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int16_t peci_wr_pkg_config(uint8_t index, uint16_t param, uint32_t data) {
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//TODO: Wait for completion?
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// Clear upstream status
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ESUCTRL0 = ESUCTRL0;
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// Clear OOB status
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ESOCTRL0 = ESOCTRL0;
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// Set upstream cycle type
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ESUCTRL1 = ESUCTRL1_OOB;
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// Set upstream tag / length[11:8]
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ESUCTRL2 = 0;
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// Set upstream length [7:0] (size of PECI data plus 3)
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ESUCTRL3 = 16;
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// Destination address (0x10 is PCH, left shifted by one)
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UDB[0] = 0x10 << 1;
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// Command code (0x01 is PECI)
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UDB[1] = 0x01;
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// Set byte count
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UDB[2] = 13;
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// Set source address (0x0F is EC, left shifted by one, or with 1)
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UDB[3] = (0x0F << 1) | 1;
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// PECI target address (0x30 is default)
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UDB[4] = 0x30;
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// PECI write length
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UDB[5] = 10;
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// PECI read length
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UDB[6] = 1;
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// PECI command (0xA5 = WrPkgConfig)
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UDB[7] = 0xA5;
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// Write host ID
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UDB[8] = 0;
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// Write index
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UDB[9] = index;
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// Write param
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UDB[10] = (uint8_t)param;
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UDB[11] = (uint8_t)(param >> 8);
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// Write data
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UDB[12] = (uint8_t)data;
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UDB[13] = (uint8_t)(data >> 8);
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UDB[14] = (uint8_t)(data >> 16);
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UDB[15] = (uint8_t)(data >> 24);
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// Set upstream enable
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ESUCTRL0 |= ESUCTRL0_ENABLE;
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// Set upstream go
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ESUCTRL0 |= ESUCTRL0_GO;
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// Wait until upstream done
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while (!(ESUCTRL0 & ESUCTRL0_DONE)) {}
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// Wait for response
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//TODO: do this asynchronously to avoid delays?
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while (!(ESOCTRL0 & ESOCTRL0_STATUS)) {}
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// Read response length
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uint8_t len = ESOCTRL4;
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if (len >= 6) {
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//TODO: verify packet type, handle PECI status
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// Received enough data for status code
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int16_t cc = (int16_t)PUTOOBDB[5];
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if (cc & 0x80) {
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return -cc;
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} else {
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return cc;
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}
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} else {
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// Did not receive enough data
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return -0x1000;
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}
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}
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#else // CONFIG_BUS_ESPI
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void peci_init(void) {
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// Allow PECI pin to be used
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GCR2 |= BIT(4);
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// Set frequency to 1MHz
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HOCTL2R = 0x01;
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// Set VTT to 1V
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PADCTLR = 0x02;
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}
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// Returns true if peci is available
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bool peci_available(void) {
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// PECI is available if PLTRST# is high
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return gpio_get(&BUF_PLT_RST_N);
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}
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// Returns true on success, false on error
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bool peci_get_temp(int16_t * data) {
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// Wait for completion
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while (HOSTAR & 1) {}
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// Clear status
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HOSTAR = HOSTAR;
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// Enable PECI, clearing data fifo's
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HOCTLR = BIT(5) | BIT(3);
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// Set address to default
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HOTRADDR = 0x30;
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// Set write length
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HOWRLR = 1;
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// Set read length
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HORDLR = 2;
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// Set command
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HOCMDR = 1;
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// Start transaction
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HOCTLR |= 1;
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// Wait for completion
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while (HOSTAR & 1) {}
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uint8_t status = HOSTAR;
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if (status & BIT(1)) {
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// Read two byte temperature data if finished successfully
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uint8_t low = HORDDR;
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uint8_t high = HORDDR;
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*data = (((int16_t)high << 8) | (int16_t)low);
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return true;
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} else {
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return false;
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}
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}
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// Returns positive completion code on success, negative completion code or
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// negative (0x1000 | status register) on PECI hardware error
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int16_t peci_wr_pkg_config(uint8_t index, uint16_t param, uint32_t data) {
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// Wait for completion
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while (HOSTAR & 1) {}
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// Clear status
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HOSTAR = HOSTAR;
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// Enable PECI, clearing data fifo's, enable AW_FCS
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HOCTLR = BIT(5) | BIT(3) | BIT(1);
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// Set address to default
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HOTRADDR = 0x30;
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// Set write length
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HOWRLR = 10;
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// Set read length
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HORDLR = 1;
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// Set command
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HOCMDR = 0xA5;
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// Write host ID
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HOWRDR = 0;
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// Write index
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HOWRDR = index;
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// Write param
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HOWRDR = (uint8_t)param;
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HOWRDR = (uint8_t)(param >> 8);
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// Write data
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HOWRDR = (uint8_t)data;
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HOWRDR = (uint8_t)(data >> 8);
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HOWRDR = (uint8_t)(data >> 16);
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HOWRDR = (uint8_t)(data >> 24);
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// Start transaction
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HOCTLR |= 1;
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// Wait for completion
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while (HOSTAR & 1) {}
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int16_t status = (int16_t)HOSTAR;
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if (status & BIT(1)) {
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int16_t cc = (int16_t)HORDDR;
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if (cc & 0x80) {
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return -cc;
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} else {
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return cc;
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}
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} else {
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return -(0x1000 | status);
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}
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}
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#endif // CONFIG_BUS_ESPI
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// PECI information can be found here: https://www.intel.com/content/dam/www/public/us/en/documents/design-guides/core-i7-lga-2011-guide.pdf
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uint8_t peci_get_fan_duty(void) {
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uint8_t duty;
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peci_on = peci_available();
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if (peci_on) {
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int16_t peci_offset = 0;
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if (peci_get_temp(&peci_offset)) {
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// Use result if finished successfully
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peci_temp = PECI_TEMP(T_JUNCTION) + (peci_offset >> 6);
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duty = fan_duty(&FAN, peci_temp);
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} else {
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// Default to 50% if there is an error
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peci_temp = 0;
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duty = PWM_DUTY(50);
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}
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} else {
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// Turn fan off if not in S0 state
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peci_temp = 0;
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duty = PWM_DUTY(0);
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}
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if (peci_on && fan_max) {
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// Override duty if fans are manually set to maximum
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duty = PWM_DUTY(100);
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} else {
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// Apply heatup and cooldown filters to duty
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duty = fan_heatup(&FAN, duty);
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duty = fan_cooldown(&FAN, duty);
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}
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TRACE("PECI temp=%d\n", peci_temp);
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return duty;
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}
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