657437e1ce
* WIP: support for new flashing API * Add SPI flashing support to tool * Add timeouts when flashing with ectool * Test SPI reading * Use chunks for SPI commands * Sanity test of flash size * Read rom in sectors * Relocate memmap region, remove PMC3 * Use ectool to flash * Remove debugging of spi command * Fix flashing over smfi
146 lines
3.9 KiB
C
146 lines
3.9 KiB
C
#include <arch/delay.h>
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#include <board/acpi.h>
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#include <board/gpio.h>
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#include <board/pmc.h>
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#include <common/debug.h>
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void pmc_init(void) {
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*(PMC_1.control) = 0x41;
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*(PMC_2.control) = 0x41;
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}
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enum PmcState {
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PMC_STATE_DEFAULT,
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PMC_STATE_WRITE,
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PMC_STATE_ACPI_READ,
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PMC_STATE_ACPI_WRITE,
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PMC_STATE_ACPI_WRITE_ADDR,
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};
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static uint8_t pmc_sci_queue = 0;
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void pmc_sci_interrupt(void) {
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// Start SCI interrupt
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gpio_set(&SCI_N, false);
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*(SCI_N.control) = GPIO_OUT;
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// Delay T_HOLD (value assumed)
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delay_us(65);
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// Stop SCI interrupt
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*(SCI_N.control) = GPIO_IN;
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gpio_set(&SCI_N, true);
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// Delay T_HOLD (value assumed)
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delay_us(65);
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}
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bool pmc_sci(struct Pmc * pmc, uint8_t sci) {
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// Set SCI queue if possible
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if (pmc_sci_queue == 0) {
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pmc_sci_queue = sci;
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// Set SCI pending bit
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pmc_set_status(pmc, pmc_status(pmc) | (1 << 5));
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// Send SCI
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pmc_sci_interrupt();
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return true;
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} else {
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return false;
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}
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}
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void pmc_event(struct Pmc * pmc) {
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static enum PmcState state = PMC_STATE_DEFAULT;
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static uint8_t state_data = 0;
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uint8_t sts = pmc_status(pmc);
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// Read command/data if available
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if (sts & PMC_STS_IBF) {
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uint8_t data = pmc_read(pmc);
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if (sts & PMC_STS_CMD) {
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TRACE("pmc cmd: %02X\n", data);
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state = PMC_STATE_DEFAULT;
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switch (data) {
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case 0x80:
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state = PMC_STATE_ACPI_READ;
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// Send SCI for IBF=0
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pmc_sci_interrupt();
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break;
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case 0x81:
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state = PMC_STATE_ACPI_WRITE;
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// Send SCI for IBF=0
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pmc_sci_interrupt();
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break;
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case 0x82:
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TRACE(" burst enable\n");
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// Set burst bit
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pmc_set_status(pmc, sts | (1 << 4));
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// Send acknowledgement byte
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state = PMC_STATE_WRITE;
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state_data = 0x90;
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break;
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case 0x83:
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TRACE(" burst disable\n");
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// Clear burst bit
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pmc_set_status(pmc, sts & ~(1 << 4));
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// Send SCI for IBF=0
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pmc_sci_interrupt();
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break;
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case 0x84:
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TRACE(" SCI queue\n");
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// Clear SCI pending bit
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pmc_set_status(pmc, sts & ~(1 << 5));
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// Send SCI queue
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state = PMC_STATE_WRITE;
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state_data = pmc_sci_queue;
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// Clear SCI queue
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pmc_sci_queue = 0;
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break;
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}
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} else {
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TRACE("pmc data: %02X\n", data);
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switch (state) {
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case PMC_STATE_ACPI_READ:
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// Send byte from ACPI space
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state = PMC_STATE_WRITE;
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state_data = acpi_read(data);
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break;
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case PMC_STATE_ACPI_WRITE:
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state = PMC_STATE_ACPI_WRITE_ADDR;
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state_data = data;
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// Send SCI for IBF=0
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pmc_sci_interrupt();
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break;
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case PMC_STATE_ACPI_WRITE_ADDR:
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state = PMC_STATE_DEFAULT;
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acpi_write(state_data, data);
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// Send SCI for IBF=0
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pmc_sci_interrupt();
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break;
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default:
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state = PMC_STATE_DEFAULT;
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break;
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}
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}
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}
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// Write data if possible
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if (!(sts & PMC_STS_OBF)) {
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switch (state) {
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case PMC_STATE_WRITE:
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TRACE("pmc write: %02X\n", state_data);
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state = PMC_STATE_DEFAULT;
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pmc_write(pmc, state_data);
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// Send SCI for OBF=1
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pmc_sci_interrupt();
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break;
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}
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}
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}
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