256 lines
7.0 KiB
C
256 lines
7.0 KiB
C
#include <arch/delay.h>
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#include <board/power.h>
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#include <board/pnp.h>
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#include <common/debug.h>
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#include <ec/gpio.h>
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// Platform does not currently support Deep Sx
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#define DEEP_SX 0
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static struct Gpio __code PCH_DPWROK_EC = GPIO(A, 3);
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static struct Gpio __code PCH_PWROK_EC = GPIO(A, 4);
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static struct Gpio __code LED_PWR = GPIO(A, 7);
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static struct Gpio __code ALL_SYS_PWRGD = GPIO(C, 0);
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static struct Gpio __code PM_PWROK = GPIO(C, 6);
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static struct Gpio __code PWR_SW_N = GPIO(D, 0);
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static struct Gpio __code BUF_PLT_RST_N = GPIO(D, 2);
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static struct Gpio __code PWR_BTN_N = GPIO(D, 5);
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static struct Gpio __code SUSWARN_N = GPIO(D, 7);
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static struct Gpio __code EC_EN = GPIO(E, 1);
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static struct Gpio __code VA_EC_EN = GPIO(E, 3);
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static struct Gpio __code DD_ON = GPIO(E, 4);
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static struct Gpio __code EC_RSMRST_N = GPIO(E, 5);
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static struct Gpio __code AC_PRESENT = GPIO(E, 7);
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static struct Gpio __code SUSC_N_PCH = GPIO(H, 1);
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static struct Gpio __code VR_ON = GPIO(H, 4);
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static struct Gpio __code SUSB_N_PCH = GPIO(H, 6);
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static struct Gpio __code SLP_SUS_N = GPIO(I, 2);
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static struct Gpio __code SUS_PWR_ACK = GPIO(J, 0);
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// VccRTC stable (55%) to RTCRST# high
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#define tPCH01 delay_ms(9)
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// VccDSW stable (95%) to RSMRST# high
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#define tPCH02 delay_ms(10)
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// VccPrimary stable (95%) to RSMRST# high
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#define tPCH03 delay_ms(10)
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// VccRTC stable (90%) to start of VccDSW voltage ramp
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#define tPCH04 delay_ms(9)
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// RTCRST# high to DSW_PWROK
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#define tPCH05 delay_us(1)
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// VccDSW 3.3 stable to VccPrimary 1.05V
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#define tPCH06 delay_us(200)
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// DSW_PWROK high to RSMRST# high
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#define tPCH07 delay_ms(0)
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// SLP_S3# de-assertion to PCH_PWROK assertion
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#define tPCH08 delay_ms(1)
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// SLP_A# high when ASW rails are stable (95%)
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#define tPCH09 delay_ms(2, 4, 8, 16) //TODO
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// PCH_PWROK low to VCCIO dropping 5%
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#define tPCH10 delay_ns(400)
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// SLP_SUS# asserting to VccPRIM dropping 5%
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#define tPCH11 delay_ns(100)
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// RSMRST# asserting to VccPRIM dropping 5%
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#define tPCH12 delay_ns(400)
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// DSW_PWROK falling to any of VccDSW, VccPRIM dropping 5%
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#define tPCH14 delay_ns(400)
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// De-assertion of RSMRST# to de-assertion of ESPI_RESET#
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#if DEEP_SX
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#define tPCH18 delay_us(90)
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#else
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#define tPCH18 delay_ms(95)
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#endif
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// DSW_PWROK assertion to SLP_SUS# de-assertion
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#define tPCH32 delay_ms(95)
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// Enable deep sleep well power
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void power_on_ds5() {
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#if DEEP_SX
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// See Figure 12-18 in Whiskey Lake Platform Design Guide
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// | VCCRTC | RTCRST# | VCCDSW_3P3 | DSW_PWROK |
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// | tPCH01---------- | | |
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// | tPCH04----------------------- | |
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// | | tPCH05-------------------------- |
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// | | | tPCH02---------------- |
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// tPCH01 and tPCH02 combined make the longest delay
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tPCH01;
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tPCH02;
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// Deep sleep well is a-ok
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gpio_set(PCH_DPWROK_EC, true);
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// Wait for deep sleep well to propogate
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tPCH32;
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#else // DEEP_SX
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// See Figure 12-19 in Whiskey Lake Platform Design Guide
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// | VCCRTC | RTCRST# | VccPRIM |
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// | tPCH01---------- | |
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// | tPCH04-------------------- |
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// tPCH04 is the ideal delay
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tPCH04;
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#endif // DEEP_SX
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}
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// Enable S5 power
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void power_on_s5() {
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#if DEEP_SX
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// See Figure 12-18 in Whiskey Lake Platform Design Guide
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// TODO
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#else // DEEP_SX
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// See Figure 12-19 in Whiskey Lake Platform Design Guide
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// TODO - signal timing graph
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// See Figure 12-25 in Whiskey Lake Platform Design Guide
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// TODO - rail timing graph
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// Enable VCCPRIM_* planes - must be enabled prior to USB power in order to
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// avoid leakage
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gpio_set(&VA_EC_EN, true);
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tPCH06;
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// Enable VDD5
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gpio_set(&DD_ON, true);
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// De-assert SUS_ACK# - TODO is this needed on non-dsx?
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gpio_set(&SUS_PWR_ACK, true);
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tPCH03;
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// Assert DSW_PWROK
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gpio_set(&PCH_DPWROK_EC, true);
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// De-assert RSMRST#
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gpio_set(&EC_RSMRST_N, true);
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// Wait for PCH stability
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tPCH18;
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// Allow processor to control SUSB# and SUSC#
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gpio_set(&EC_EN, true);
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#endif // DEEP_SX
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}
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void power_off_s5() {
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#if DEEP_SX
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// TODO
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#else // DEEP_SX
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// De-assert SYS_PWROK
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gpio_set(&PCH_PWROK_EC, false);
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// De-assert PCH_PWROK
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gpio_set(&PM_PWROK, false);
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// Block processor from controlling SUSB# and SUSC#
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gpio_set(&EC_EN, false);
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// De-assert RSMRST#
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gpio_set(&EC_RSMRST_N, false);
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// Disable VDD5
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gpio_set(&DD_ON, false);
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tPCH12;
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// Disable VCCPRIM_* planes
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gpio_set(&VA_EC_EN, false);
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// De-assert DSW_PWROK
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gpio_set(&PCH_DPWROK_EC, false);
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tPCH14;
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#endif // DEEP_SX
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}
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enum PowerState {
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POWER_STATE_DEFAULT,
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POWER_STATE_DS5,
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POWER_STATE_S5,
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POWER_STATE_DS3,
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POWER_STATE_S3,
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POWER_STATE_S0,
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};
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void power_event(void) {
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static enum PowerState state = POWER_STATE_DEFAULT;
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// Always switch to ds5 if EC is running
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if (state == POWER_STATE_DEFAULT) {
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power_on_ds5();
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state = POWER_STATE_DS5;
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//TODO: Logic for switching from ds5 to s5
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power_on_s5();
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state = POWER_STATE_S5;
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}
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// Read power button state
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static bool last = true;
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bool new = gpio_get(&PWR_SW_N);
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if (!new && last) {
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// Ensure press is not spurious
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delay_ms(10);
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if (gpio_get(&PWR_SW_N) != new) {
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DEBUG("Spurious press\n");
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return;
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}
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DEBUG("Power switch press\n");
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}
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#if LEVEL >= LEVEL_DEBUG
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else if (new && !last) {
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DEBUG("Power switch release\n");
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}
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#endif
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// Send power signal to PCH
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gpio_set(&PWR_BTN_N, new);
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#if DEEP_SX
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//TODO
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#else // DEEP_SX
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//TODO: set power state as necessary
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// If system power is good
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if (gpio_get(&ALL_SYS_PWRGD)) {
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DEBUG("ALL_SYS_PWRGD asserted\n");
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// Allow H_VR_READY to set PCH_PWROK
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gpio_set(&PM_PWROK, true);
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// OEM defined delay from ALL_SYS_PWRGD to SYS_PWROK - TODO
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delay_ms(10);
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// Assert SYS_PWROK, system can finally perform PLT_RST# and boot
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gpio_set(&PCH_PWROK_EC, true);
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} else {
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DEBUG("ALL_SYS_PWRGD de-asserted\n");
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// De-assert SYS_PWROK
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gpio_set(&PCH_PWROK_EC, false);
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// De-assert PCH_PWROK
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gpio_set(&PM_PWROK, false);
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}
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static bool rst_old = false;
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bool rst_new = gpio_get(&BUF_PLT_RST_N);
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if (!rst_old && rst_new) {
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// LPC was just reset, enable PNP devices
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pnp_enable();
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//TODO: reset KBC and touchpad states
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}
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// EC must keep VccPRIM powered if SUSPWRDNACK is de-asserted low or system
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// state is S3
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bool primary = !gpio_get(&SUSWARN_N) || !gpio_get(&SUSB_N_PCH);
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if (primary) {
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if (state == POWER_STATE_DS5) {
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power_on_s5();
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state = POWER_STATE_DS5;
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}
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} else {
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if (state == POWER_STATE_S5) {
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power_off_s5();
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state = POWER_STATE_DS5;
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}
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}
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#endif // DEEP_SX
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}
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