Add lemp13
This commit is contained in:
Jeremy Soller
parent
bd4d0333b6
commit
14aee2d11a
@ -26,6 +26,7 @@ features apply to your model and firmware version, see the
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- tgl: Fixed TBT ACPI
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- Fixed RTC being reset on boot during February 29th
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- addw4: Added initial release of open firmware with System76 EC
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- lemp13: Added initial release of open firmware with System76 EC
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## 2024-01-18
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@ -33,6 +33,7 @@
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- [lemp10](./lemp10) - System76 Lemur Pro (lemp10)
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- [lemp11](./lemp11) - System76 Lemur Pro (lemp11)
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- [lemp12](./lemp12) - System76 Lemur Pro (lemp12)
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- [lemp13](./lemp13) - System76 Lemur Pro (lemp13)
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- [lemp9](./lemp9) - System76 Lemur Pro (lemp9)
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- [oryp10](./oryp10) - System76 Oryx Pro (oryp10)
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- [oryp11](./oryp11) - System76 Oryx Pro (oryp11)
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@ -9,4 +9,4 @@
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- HAP: false
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- [ME](./me.rom)
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- Size: 4824 KB
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- Version: 16.1.25.2164
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- Version: 16.1.25.2166
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BIN
models/lemp13/IntelGopDriver.efi
(Stored with Git LFS)
Normal file
BIN
models/lemp13/IntelGopDriver.efi
(Stored with Git LFS)
Normal file
Binary file not shown.
9
models/lemp13/IntelGopDriver.inf
Normal file
9
models/lemp13/IntelGopDriver.inf
Normal file
@ -0,0 +1,9 @@
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[Defines]
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INF_VERSION = 0x00010005
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BASE_NAME = IntelGopDriver
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FILE_GUID = 767222f4-a9f4-41ba-9faa-edaa1405a486
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MODULE_TYPE = UEFI_DRIVER
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VERSION_STRING = 1.0
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[Binaries.X64]
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PE32|IntelGopDriver.efi|*
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6489
models/lemp13/MeteorLakeFspBinPkg/Fsp.bsf
Normal file
6489
models/lemp13/MeteorLakeFspBinPkg/Fsp.bsf
Normal file
File diff suppressed because it is too large
Load Diff
BIN
models/lemp13/MeteorLakeFspBinPkg/Fsp.fd
(Stored with Git LFS)
Normal file
BIN
models/lemp13/MeteorLakeFspBinPkg/Fsp.fd
(Stored with Git LFS)
Normal file
Binary file not shown.
114
models/lemp13/MeteorLakeFspBinPkg/FspPkgPcdShare.dsc
Normal file
114
models/lemp13/MeteorLakeFspBinPkg/FspPkgPcdShare.dsc
Normal file
@ -0,0 +1,114 @@
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## @file
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# Platform description for DynamicEx PCDs, defined in FSP Package
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# and shared with Board Package.
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#
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# @copyright
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# INTEL CONFIDENTIAL
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# Copyright 2018 - 2021 Intel Corporation.
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#
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# The source code contained or described herein and all documents related to the
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# source code ("Material") are owned by Intel Corporation or its suppliers or
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# licensors. Title to the Material remains with Intel Corporation or its suppliers
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# and licensors. The Material may contain trade secrets and proprietary and
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# confidential information of Intel Corporation and its suppliers and licensors,
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# and is protected by worldwide copyright and trade secret laws and treaty
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# provisions. No part of the Material may be used, copied, reproduced, modified,
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# published, uploaded, posted, transmitted, distributed, or disclosed in any way
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# without Intel's prior express written permission.
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#
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# No license under any patent, copyright, trade secret or other intellectual
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# property right is granted to or conferred upon you by disclosure or delivery
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# of the Materials, either expressly, by implication, inducement, estoppel or
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# otherwise. Any license under such intellectual property rights must be
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# express and approved by Intel in writing.
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#
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# Unless otherwise agreed by Intel in writing, you may not remove or alter
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# this notice or any other notice embedded in Materials by Intel or
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# Intel's suppliers or licensors in any way.
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#
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# This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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# "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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# the terms of your license agreement with Intel or your vendor. This file may
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# be modified by the user, subject to additional terms of the license agreement.
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#
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# @par Specification
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##
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[PcdsDynamicExDefault]
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## Specifies max supported number of Logical Processors.
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# @Prompt Configure max supported number of Logical Processorss
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gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|16
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gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|0xC0000000
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gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000
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## Specifies the base address of the first microcode Patch in the microcode Region.
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# @Prompt Microcode Region base address.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0
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## Specifies the size of the microcode Region.
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# @Prompt Microcode Region size.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0
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## Specifies the AP wait loop state during POST phase.
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# The value is defined as below.
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# 1: Place AP in the Hlt-Loop state.
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# 2: Place AP in the Mwait-Loop state.
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# 3: Place AP in the Run-Loop state.
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# @Prompt The AP wait loop state.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2
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## Specifies the AP target C-state for Mwait during POST phase.
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# The default value 0 means C1 state.
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# The value is defined as below.<BR><BR>
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# @Prompt The specified AP target C-state for Mwait.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0
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#
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# Enable ACPI S3 support in FSP by default
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#
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gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable|1
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## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DATA.
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# @Prompt The pointer to a CPU S3 data buffer.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuS3DataAddress|0x00
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## As input, specifies user's desired settings for enabling/disabling processor features.
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## As output, specifies actual settings for processor features, each bit corresponding to a specific feature.
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# @Prompt As input, specifies user's desired processor feature settings. As output, specifies actual processor feature settings.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSetting|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
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## Contains the size of memory required when CPU processor trace is enabled.<BR><BR>
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# Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.<BR><BR>
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# @Prompt The memory size used for processor trace if processor trace is enabled.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize|0x0
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## Contains the processor trace output scheme when CPU processor trace is enabled.<BR><BR>
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# Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.<BR><BR>
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# @Prompt The processor trace output scheme used when processor trace is enabled.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme|0x0
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## Indicates processor feature capabilities, each bit corresponding to a specific feature.
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# @Prompt Processor feature capabilities.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesCapability|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
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# Set SEV-ES defaults
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gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase|0
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gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize|0
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gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled|0
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## This dynamic PCD hold an address to point to private data structure used in DxeS3BootScriptLib library
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# instance which records the S3 boot script table start address, length, etc. To introduce this PCD is
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# only for DxeS3BootScriptLib instance implementation purpose. The platform developer should make sure the
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# default value is set to Zero. And the PCD is assumed ONLY to be accessed in DxeS3BootScriptLib Library.
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# @Prompt S3 Boot Script Table Private Data pointer.
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gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0
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## This dynamic PCD hold an address to point to private data structure SMM copy used in DxeS3BootScriptLib library
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# instance which records the S3 boot script table start address, length, etc. To introduce this PCD is
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# only for DxeS3BootScriptLib instance implementation purpose. The platform developer should make sure the
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# default value is set to Zero. And the PCD is assumed ONLY to be accessed in DxeS3BootScriptLib Library.
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# @Prompt S3 Boot Script Table Private Smm Data pointer.
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# @ValidList 0x80000001 | 0x0
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gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr|0
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@ -0,0 +1,55 @@
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/** @file
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Intel Firmware Version Info (FVI) related definitions.
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@todo update document/spec reference
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Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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@par Specification Reference:
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System Management BIOS (SMBIOS) Reference Specification v3.0.0 dated 2015-Feb-12
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http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.0.0.pdf
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**/
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#ifndef __FIRMWARE_VERSION_INFO_H__
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#define __FIRMWARE_VERSION_INFO_H__
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#include <IndustryStandard/SmBios.h>
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#define INTEL_FIRMWARE_VERSION_INFO_GROUP_NAME "Firmware Version Info"
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#define INTEL_FVI_SMBIOS_TYPE 0xDD
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#pragma pack(1)
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///
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/// Firmware Version Structure
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///
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typedef struct {
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UINT8 MajorVersion;
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UINT8 MinorVersion;
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UINT8 Revision;
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UINT16 BuildNumber;
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} INTEL_FIRMWARE_VERSION;
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///
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/// Firmware Version Info (FVI) Structure
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///
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typedef struct {
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SMBIOS_TABLE_STRING ComponentName; ///< String Index of Component Name
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SMBIOS_TABLE_STRING VersionString; ///< String Index of Version String
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INTEL_FIRMWARE_VERSION Version; ///< Firmware version
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} INTEL_FIRMWARE_VERSION_INFO;
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///
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/// SMBIOS OEM Type Intel Firmware Version Info (FVI) Structure
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///
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typedef struct {
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SMBIOS_STRUCTURE Header; ///< SMBIOS structure header
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UINT8 Count; ///< Number of FVI entries in this structure
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INTEL_FIRMWARE_VERSION_INFO Fvi[1]; ///< FVI structure(s)
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} SMBIOS_TABLE_TYPE_OEM_INTEL_FVI;
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#pragma pack()
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#endif
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@ -0,0 +1,80 @@
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/** @file
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Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef _FSP_PRODUCER_DATA_HEADER_H_
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#define _FSP_PRODUCER_DATA_HEADER_H_
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#include <Guid/FspHeaderFile.h>
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#define BUILD_TIME_STAMP_SIZE 12
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//
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// FSP Header Data structure from FspHeader driver.
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//
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#pragma pack(1)
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///
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/// FSP Producer Data Subtype - 1
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///
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typedef struct {
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///
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/// Byte 0x00: Length of this FSP producer data type record.
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///
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UINT16 Length;
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///
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/// Byte 0x02: FSP producer data type.
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///
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UINT8 Type;
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///
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/// Byte 0x03: Revision of this FSP producer data type.
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///
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UINT8 Revision;
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///
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/// Byte 0x04: 4 byte field of RC version which is used to build this FSP image.
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///
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UINT32 RcVersion;
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///
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/// Byte 0x08: Represents the build time stamp "YYYYMMDDHHMM".
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///
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UINT8 BuildTimeStamp[BUILD_TIME_STAMP_SIZE];
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} FSP_PRODUCER_DATA_TYPE1;
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///
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/// FSP Producer Data Subtype - 2
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///
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typedef struct {
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///
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/// Byte 0x00: Length of this FSP producer data type record.
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///
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UINT16 Length;
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///
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/// Byte 0x02: FSP producer data type.
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///
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UINT8 Type;
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///
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/// Byte 0x03: Revision of this FSP producer data type.
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///
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UINT8 Revision;
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///
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/// Byte 0x04: 4 byte field of Mrc version which is used to build this FSP image.
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///
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UINT8 MrcVersion [4];
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} FSP_PRODUCER_DATA_TYPE2;
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typedef struct {
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FSP_INFO_HEADER FspInfoHeader;
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FSP_INFO_EXTENDED_HEADER FspInfoExtendedHeader;
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FSP_PRODUCER_DATA_TYPE1 FspProduceDataType1;
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FSP_PRODUCER_DATA_TYPE2 FspProduceDataType2;
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FSP_PATCH_TABLE FspPatchTable;
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} FSP_PRODUCER_DATA_TABLES;
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#pragma pack()
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#endif // _FSP_PRODUCER_DATA_HEADER_H
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48
models/lemp13/MeteorLakeFspBinPkg/Include/FspUpd.h
Normal file
48
models/lemp13/MeteorLakeFspBinPkg/Include/FspUpd.h
Normal file
@ -0,0 +1,48 @@
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/** @file
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Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
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|
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Redistribution and use in source and binary forms, with or without modification,
|
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are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
* Redistributions in binary form must reproduce the above copyright notice, this
|
||||
list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
|
||||
* Neither the name of Intel Corporation nor the names of its contributors may
|
||||
be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
This file is automatically generated. Please do NOT modify !!!
|
||||
|
||||
**/
|
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|
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#ifndef __FSPUPD_H__
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#define __FSPUPD_H__
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#include <FspEas.h>
|
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#pragma pack(1)
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#define FSPT_UPD_SIGNATURE 0x545F4450554C544D /* 'MTLUPD_T' */
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#define FSPM_UPD_SIGNATURE 0x4D5F4450554C544D /* 'MTLUPD_M' */
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#define FSPS_UPD_SIGNATURE 0x535F4450554C544D /* 'MTLUPD_S' */
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#pragma pack()
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#endif
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5134
models/lemp13/MeteorLakeFspBinPkg/Include/FspmUpd.h
Normal file
5134
models/lemp13/MeteorLakeFspBinPkg/Include/FspmUpd.h
Normal file
File diff suppressed because it is too large
Load Diff
4577
models/lemp13/MeteorLakeFspBinPkg/Include/FspsUpd.h
Normal file
4577
models/lemp13/MeteorLakeFspBinPkg/Include/FspsUpd.h
Normal file
File diff suppressed because it is too large
Load Diff
420
models/lemp13/MeteorLakeFspBinPkg/Include/FsptUpd.h
Normal file
420
models/lemp13/MeteorLakeFspBinPkg/Include/FsptUpd.h
Normal file
@ -0,0 +1,420 @@
|
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/** @file
|
||||
|
||||
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
* Redistributions in binary form must reproduce the above copyright notice, this
|
||||
list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
|
||||
* Neither the name of Intel Corporation nor the names of its contributors may
|
||||
be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
This file is automatically generated. Please do NOT modify !!!
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __FSPTUPD_H__
|
||||
#define __FSPTUPD_H__
|
||||
|
||||
#include <FspUpd.h>
|
||||
|
||||
#pragma pack(1)
|
||||
|
||||
|
||||
/** Fsp T Core UPD
|
||||
**/
|
||||
typedef struct {
|
||||
|
||||
/** Offset 0x0040
|
||||
**/
|
||||
UINT32 MicrocodeRegionBase;
|
||||
|
||||
/** Offset 0x0044
|
||||
**/
|
||||
UINT32 MicrocodeRegionSize;
|
||||
|
||||
/** Offset 0x0048
|
||||
**/
|
||||
UINT32 CodeRegionBase;
|
||||
|
||||
/** Offset 0x004C
|
||||
**/
|
||||
UINT32 CodeRegionSize;
|
||||
|
||||
/** Offset 0x0050
|
||||
**/
|
||||
UINT8 Reserved[16];
|
||||
} FSPT_CORE_UPD;
|
||||
|
||||
/** Fsp T Configuration
|
||||
**/
|
||||
typedef struct {
|
||||
|
||||
/** Offset 0x0060 - PcdSerialIoUartDebugEnable
|
||||
Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP.
|
||||
0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
|
||||
**/
|
||||
UINT8 PcdSerialIoUartDebugEnable;
|
||||
|
||||
/** Offset 0x0061 - PcdSerialIoUartNumber
|
||||
Select SerialIo Uart Controller for debug.
|
||||
0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
|
||||
**/
|
||||
UINT8 PcdSerialIoUartNumber;
|
||||
|
||||
/** Offset 0x0062 - PcdSerialIoUartMode - FSPT
|
||||
Select SerialIo Uart Controller mode
|
||||
0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
|
||||
4:SerialIoUartSkipInit
|
||||
**/
|
||||
UINT8 PcdSerialIoUartMode;
|
||||
|
||||
/** Offset 0x0063 - PcdSerialIoUartPowerGating - FSPT
|
||||
Select SerialIo Uart Controller Powergating mode
|
||||
0:Disabled, 1:Enabled, 2:Auto
|
||||
**/
|
||||
UINT8 PcdSerialIoUartPowerGating;
|
||||
|
||||
/** Offset 0x0064 - PcdSerialIoUartBaudRate - FSPT
|
||||
Set default BaudRate Supported from 0 - default to 6000000
|
||||
**/
|
||||
UINT32 PcdSerialIoUartBaudRate;
|
||||
|
||||
/** Offset 0x0068 - Pci Express Base Address
|
||||
Base address to be programmed for Pci Express
|
||||
**/
|
||||
UINT64 PcdPciExpressBaseAddress;
|
||||
|
||||
/** Offset 0x0070 - Pci Express Region Length
|
||||
Region Length to be programmed for Pci Express
|
||||
**/
|
||||
UINT32 PcdPciExpressRegionLength;
|
||||
|
||||
/** Offset 0x0074 - PcdSerialIoUartParity - FSPT
|
||||
Set default Parity.
|
||||
0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
|
||||
**/
|
||||
UINT8 PcdSerialIoUartParity;
|
||||
|
||||
/** Offset 0x0075 - PcdSerialIoUartDataBits - FSPT
|
||||
Set default word length. 0: Default, 5,6,7,8
|
||||
**/
|
||||
UINT8 PcdSerialIoUartDataBits;
|
||||
|
||||
/** Offset 0x0076 - PcdSerialIoUartStopBits - FSPT
|
||||
Set default stop bits.
|
||||
0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits
|
||||
**/
|
||||
UINT8 PcdSerialIoUartStopBits;
|
||||
|
||||
/** Offset 0x0077 - PcdSerialIoUartAutoFlow - FSPT
|
||||
Enables UART hardware flow control, CTS and RTS lines.
|
||||
0: Disable, 1:Enable
|
||||
**/
|
||||
UINT8 PcdSerialIoUartAutoFlow;
|
||||
|
||||
/** Offset 0x0078 - PcdSerialIoUartRxPinMux - FSPT
|
||||
Select RX pin muxing for SerialIo UART used for debug
|
||||
**/
|
||||
UINT32 PcdSerialIoUartRxPinMux;
|
||||
|
||||
/** Offset 0x007C - PcdSerialIoUartTxPinMux - FSPT
|
||||
Select TX pin muxing for SerialIo UART used for debug
|
||||
**/
|
||||
UINT32 PcdSerialIoUartTxPinMux;
|
||||
|
||||
/** Offset 0x0080 - PcdSerialIoUartRtsPinMux - FSPT
|
||||
Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
|
||||
for possible values.
|
||||
**/
|
||||
UINT32 PcdSerialIoUartRtsPinMux;
|
||||
|
||||
/** Offset 0x0084 - PcdSerialIoUartCtsPinMux - FSPT
|
||||
Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS*
|
||||
for possible values.
|
||||
**/
|
||||
UINT32 PcdSerialIoUartCtsPinMux;
|
||||
|
||||
/** Offset 0x0088 - PcdSerialIoUartDebugMmioBase - FSPT
|
||||
Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode
|
||||
= SerialIoUartPci.
|
||||
**/
|
||||
UINT32 PcdSerialIoUartDebugMmioBase;
|
||||
|
||||
/** Offset 0x008C - PcdSerialIoUartDebugPciCfgBase - FSPT
|
||||
Specify PciCfgBase address. Allows for SerialIO UART functionality outside Bus 0
|
||||
**/
|
||||
UINT32 PcdSerialIoUartDebugPciCfgBase;
|
||||
|
||||
/** Offset 0x0090 - PcdLpcUartDebugEnable
|
||||
Enable to initialize LPC Uart device in FSP.
|
||||
0:Disable, 1:Enable
|
||||
**/
|
||||
UINT8 PcdLpcUartDebugEnable;
|
||||
|
||||
/** Offset 0x0091 - Debug Interfaces
|
||||
Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub,
|
||||
BIT2 - Not used.
|
||||
**/
|
||||
UINT8 PcdDebugInterfaceFlags;
|
||||
|
||||
/** Offset 0x0092 - PcdSerialDebugLevel
|
||||
Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
|
||||
Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
|
||||
Info & Verbose.
|
||||
0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load
|
||||
Error Warnings and Info, 5:Load Error Warnings Info and Verbose
|
||||
**/
|
||||
UINT8 PcdSerialDebugLevel;
|
||||
|
||||
/** Offset 0x0093 - ISA Serial Base selection
|
||||
Select ISA Serial Base address. Default is 0x3F8.
|
||||
0:0x3F8, 1:0x2F8
|
||||
**/
|
||||
UINT8 PcdIsaSerialUartBase;
|
||||
|
||||
/** Offset 0x0094 - PcdSerialIo2ndUartEnable
|
||||
Enable Additional SerialIo Uart device in FSP.
|
||||
0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
|
||||
**/
|
||||
UINT8 PcdSerialIo2ndUartEnable;
|
||||
|
||||
/** Offset 0x0095 - PcdSerialIo2ndUartNumber
|
||||
Select SerialIo Uart Controller Number
|
||||
0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
|
||||
**/
|
||||
UINT8 PcdSerialIo2ndUartNumber;
|
||||
|
||||
/** Offset 0x0096 - PcdSerialIo2ndUartMode - FSPT
|
||||
Select SerialIo Uart Controller mode
|
||||
0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
|
||||
4:SerialIoUartSkipInit
|
||||
**/
|
||||
UINT8 PcdSerialIo2ndUartMode;
|
||||
|
||||
/** Offset 0x0097
|
||||
**/
|
||||
UINT8 Rsvd020[1];
|
||||
|
||||
/** Offset 0x0098 - PcdSerialIo2ndUartBaudRate - FSPT
|
||||
Set default BaudRate Supported from 0 - default to 6000000
|
||||
**/
|
||||
UINT32 PcdSerialIo2ndUartBaudRate;
|
||||
|
||||
/** Offset 0x009C - PcdSerialIo2ndUartParity - FSPT
|
||||
Set default Parity.
|
||||
0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
|
||||
**/
|
||||
UINT8 PcdSerialIo2ndUartParity;
|
||||
|
||||
/** Offset 0x009D - PcdSerialIo2ndUartDataBits - FSPT
|
||||
Set default word length. 0: Default, 5,6,7,8
|
||||
**/
|
||||
UINT8 PcdSerialIo2ndUartDataBits;
|
||||
|
||||
/** Offset 0x009E - PcdSerialIo2ndUartStopBits - FSPT
|
||||
Set default stop bits.
|
||||
0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits
|
||||
**/
|
||||
UINT8 PcdSerialIo2ndUartStopBits;
|
||||
|
||||
/** Offset 0x009F - PcdSerialIo2ndUartAutoFlow - FSPT
|
||||
Enables UART hardware flow control, CTS and RTS lines.
|
||||
0: Disable, 1:Enable
|
||||
**/
|
||||
UINT8 PcdSerialIo2ndUartAutoFlow;
|
||||
|
||||
/** Offset 0x00A0 - PcdSerialIo2ndUartRxPinMux - FSPT
|
||||
Select RX pin muxing for SerialIo UART
|
||||
**/
|
||||
UINT32 PcdSerialIo2ndUartRxPinMux;
|
||||
|
||||
/** Offset 0x00A4 - PcdSerialIo2ndUartTxPinMux - FSPT
|
||||
Select TX pin muxing for SerialIo UART
|
||||
**/
|
||||
UINT32 PcdSerialIo2ndUartTxPinMux;
|
||||
|
||||
/** Offset 0x00A8 - PcdSerialIo2ndUartRtsPinMux - FSPT
|
||||
Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
|
||||
for possible values.
|
||||
**/
|
||||
UINT32 PcdSerialIo2ndUartRtsPinMux;
|
||||
|
||||
/** Offset 0x00AC - PcdSerialIo2ndUartCtsPinMux - FSPT
|
||||
Select SerialIo Uart Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS*
|
||||
for possible values.
|
||||
**/
|
||||
UINT32 PcdSerialIo2ndUartCtsPinMux;
|
||||
|
||||
/** Offset 0x00B0 - PcdSerialIo2ndUartMmioBase - FSPT
|
||||
Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIo2ndUartMode
|
||||
= SerialIoUartPci.
|
||||
**/
|
||||
UINT32 PcdSerialIo2ndUartMmioBase;
|
||||
|
||||
/** Offset 0x00B4 - PcdSerialIo2ndUartPciCfgBase - FSPT
|
||||
Specify PciCfgBase address. Allows for SerialIO UART functionality outside Bus 0
|
||||
**/
|
||||
UINT32 PcdSerialIo2ndUartPciCfgBase;
|
||||
|
||||
/** Offset 0x00B8
|
||||
**/
|
||||
UINT32 TopMemoryCacheSize;
|
||||
|
||||
/** Offset 0x00BC - FspDebugHandler
|
||||
<b>Optional</b> pointer to the boot loader's implementation of FSP_DEBUG_HANDLER.
|
||||
**/
|
||||
UINT32 FspDebugHandler;
|
||||
|
||||
/** Offset 0x00C0 - Serial Io SPI Chip Select Polarity
|
||||
Sets polarity for each chip Select. Available options: 0:SerialIoSpiCsActiveLow,
|
||||
1:SerialIoSpiCsActiveHigh
|
||||
**/
|
||||
UINT8 PcdSerialIoSpiCsPolarity[2];
|
||||
|
||||
/** Offset 0x00C2 - Serial Io SPI Chip Select Enable
|
||||
0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled
|
||||
**/
|
||||
UINT8 PcdSerialIoSpiCsEnable[2];
|
||||
|
||||
/** Offset 0x00C4 - Serial Io SPI Device Mode
|
||||
When mode is set to Pci, controller is initalized in early stage. Available modes:
|
||||
0:SerialIoSpiDisabled, 1:SerialIoSpiPci.
|
||||
**/
|
||||
UINT8 PcdSerialIoSpiMode;
|
||||
|
||||
/** Offset 0x00C5 - Serial Io SPI Default Chip Select Output
|
||||
Sets Default CS as Output. Available options: 0:CS0, 1:CS1
|
||||
**/
|
||||
UINT8 PcdSerialIoSpiDefaultCsOutput;
|
||||
|
||||
/** Offset 0x00C6 - Serial Io SPI Default Chip Select Mode HW/SW
|
||||
Sets Default CS Mode Hardware or Software. Available options: 0:HW, 1:SW
|
||||
**/
|
||||
UINT8 PcdSerialIoSpiCsMode;
|
||||
|
||||
/** Offset 0x00C7 - Serial Io SPI Default Chip Select State Low/High
|
||||
Sets Default CS State Low or High. Available options: 0:Low, 1:High
|
||||
**/
|
||||
UINT8 PcdSerialIoSpiCsState;
|
||||
|
||||
/** Offset 0x00C8 - Serial Io SPI Device Number
|
||||
Select which Serial Io SPI controller is initalized in early stage.
|
||||
**/
|
||||
UINT8 PcdSerialIoSpiNumber;
|
||||
|
||||
/** Offset 0x00C9
|
||||
**/
|
||||
UINT8 Rsvd030[3];
|
||||
|
||||
/** Offset 0x00CC - Serial Io SPI Device MMIO Base
|
||||
Assigns MMIO for Serial Io SPI controller usage in early stage.
|
||||
**/
|
||||
UINT32 PcdSerialIoSpiMmioBase;
|
||||
|
||||
/** Offset 0x00D0 - Serial IO SPI CS Pin Muxing
|
||||
Select SerialIo SPI CS pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CS* for
|
||||
possible values.
|
||||
**/
|
||||
UINT32 PcdSerialIoSpiCsPinMux[2];
|
||||
|
||||
/** Offset 0x00D8 - Serial IO SPI CLK Pin Muxing
|
||||
Select SerialIo SPI CLK pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CLK* for
|
||||
possible values.
|
||||
**/
|
||||
UINT32 PcdSerialIoSpiClkPinMux;
|
||||
|
||||
/** Offset 0x00DC - Serial IO SPI MISO Pin Muxing
|
||||
Select SerialIo SPI MISO pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MISO*
|
||||
for possible values.
|
||||
**/
|
||||
UINT32 PcdSerialIoSpiMisoPinMux;
|
||||
|
||||
/** Offset 0x00E0 - Serial IO SPI MOSI Pin Muxing
|
||||
Select SerialIo SPI MOSI pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MOSI*
|
||||
for possible values.
|
||||
**/
|
||||
UINT32 PcdSerialIoSpiMosiPinMux;
|
||||
|
||||
/** Offset 0x00E4 - Serial Io I2C Device MMIO Base
|
||||
Assigns MMIO for Serial Io I2C controller usage in early stage.
|
||||
**/
|
||||
UINT32 PcdSerialIoI2cMmioBase;
|
||||
|
||||
/** Offset 0x00E8 - Serial Io I2C Sda Gpio Pin
|
||||
Select SerialIo I2C Rts pin. Refer to GPIO_*_MUXING_SERIALIO_I2C*_SDA* for possible values.
|
||||
**/
|
||||
UINT32 PcdSerialIoI2cSdaPin;
|
||||
|
||||
/** Offset 0x00EC - Serial Io I2C Scl Gpio Pin
|
||||
Select SerialIo I2C Cts pin. Refer to GPIO_*_MUXING_SERIALIO_I2C*_SCL* for possible values.
|
||||
**/
|
||||
UINT32 PcdSerialIoI2cSclPin;
|
||||
|
||||
/** Offset 0x00F0 - Serial Io I2C Gpio Pad termination
|
||||
0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
|
||||
0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,... pads termination
|
||||
respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on.
|
||||
**/
|
||||
UINT8 PcdSerialIoI2cPadsTerm;
|
||||
|
||||
/** Offset 0x00F1 - Serial Io I2c Controller Number
|
||||
Select SerialIo I2C Controller number to be intilizaed during early boot. Default is 0xFF
|
||||
0:SerialIoI2c0, 1:SerialIoI2c1, 2:SerialIoI2c2, 0xFF:Disable
|
||||
**/
|
||||
UINT8 PcdSerialIoI2cNumber;
|
||||
|
||||
/** Offset 0x00F2
|
||||
**/
|
||||
UINT8 ReservedFsptUpd1[6];
|
||||
} FSP_T_CONFIG;
|
||||
|
||||
/** Fsp T UPD Configuration
|
||||
**/
|
||||
typedef struct {
|
||||
|
||||
/** Offset 0x0000
|
||||
**/
|
||||
FSP_UPD_HEADER FspUpdHeader;
|
||||
|
||||
/** Offset 0x0020
|
||||
**/
|
||||
FSPT_ARCH_UPD FsptArchUpd;
|
||||
|
||||
/** Offset 0x0040
|
||||
**/
|
||||
FSPT_CORE_UPD FsptCoreUpd;
|
||||
|
||||
/** Offset 0x0060
|
||||
**/
|
||||
FSP_T_CONFIG FsptConfig;
|
||||
|
||||
/** Offset 0x00F8
|
||||
**/
|
||||
UINT8 Rsvd3[6];
|
||||
|
||||
/** Offset 0x00FE
|
||||
**/
|
||||
UINT16 UpdTerminator;
|
||||
} FSPT_UPD;
|
||||
|
||||
#pragma pack()
|
||||
|
||||
#endif
|
||||
349
models/lemp13/MeteorLakeFspBinPkg/Include/GpioConfig.h
Normal file
349
models/lemp13/MeteorLakeFspBinPkg/Include/GpioConfig.h
Normal file
@ -0,0 +1,349 @@
|
||||
/** @file
|
||||
Header file for GpioConfig structure used by GPIO library.
|
||||
|
||||
@copyright
|
||||
INTEL CONFIDENTIAL
|
||||
Copyright 2014 - 2017 Intel Corporation.
|
||||
|
||||
The source code contained or described herein and all documents related to the
|
||||
source code ("Material") are owned by Intel Corporation or its suppliers or
|
||||
licensors. Title to the Material remains with Intel Corporation or its suppliers
|
||||
and licensors. The Material may contain trade secrets and proprietary and
|
||||
confidential information of Intel Corporation and its suppliers and licensors,
|
||||
and is protected by worldwide copyright and trade secret laws and treaty
|
||||
provisions. No part of the Material may be used, copied, reproduced, modified,
|
||||
published, uploaded, posted, transmitted, distributed, or disclosed in any way
|
||||
without Intel's prior express written permission.
|
||||
|
||||
No license under any patent, copyright, trade secret or other intellectual
|
||||
property right is granted to or conferred upon you by disclosure or delivery
|
||||
of the Materials, either expressly, by implication, inducement, estoppel or
|
||||
otherwise. Any license under such intellectual property rights must be
|
||||
express and approved by Intel in writing.
|
||||
|
||||
Unless otherwise agreed by Intel in writing, you may not remove or alter
|
||||
this notice or any other notice embedded in Materials by Intel or
|
||||
Intel's suppliers or licensors in any way.
|
||||
|
||||
This file contains an 'Intel Peripheral Driver' and is uniquely identified as
|
||||
"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
|
||||
the terms of your license agreement with Intel or your vendor. This file may
|
||||
be modified by the user, subject to additional terms of the license agreement.
|
||||
|
||||
@par Specification Reference:
|
||||
**/
|
||||
#ifndef _GPIO_CONFIG_H_
|
||||
#define _GPIO_CONFIG_H_
|
||||
|
||||
#pragma pack(push, 1)
|
||||
|
||||
///
|
||||
/// For any GpioPad usage in code use GPIO_PAD type
|
||||
///
|
||||
typedef UINT32 GPIO_PAD;
|
||||
|
||||
|
||||
///
|
||||
/// For any GpioGroup usage in code use GPIO_GROUP type
|
||||
///
|
||||
typedef UINT32 GPIO_GROUP;
|
||||
|
||||
/**
|
||||
GPIO configuration structure used for pin programming.
|
||||
Structure contains fields that can be used to configure pad.
|
||||
**/
|
||||
typedef struct {
|
||||
/**
|
||||
Pad Mode
|
||||
Pad can be set as GPIO or one of its native functions.
|
||||
When in native mode setting Direction (except Inversion), OutputState,
|
||||
InterruptConfig, Host Software Pad Ownership and OutputStateLock are unnecessary.
|
||||
Refer to definition of GPIO_PAD_MODE.
|
||||
Refer to EDS for each native mode according to the pad.
|
||||
**/
|
||||
UINT32 PadMode : 5;
|
||||
/**
|
||||
Host Software Pad Ownership
|
||||
Set pad to ACPI mode or GPIO Driver Mode.
|
||||
Refer to definition of GPIO_HOSTSW_OWN.
|
||||
**/
|
||||
UINT32 HostSoftPadOwn : 2;
|
||||
/**
|
||||
GPIO Direction
|
||||
Can choose between In, In with inversion, Out, both In and Out, both In with inversion and out or disabling both.
|
||||
Refer to definition of GPIO_DIRECTION for supported settings.
|
||||
**/
|
||||
UINT32 Direction : 6;
|
||||
/**
|
||||
Output State
|
||||
Set Pad output value.
|
||||
Refer to definition of GPIO_OUTPUT_STATE for supported settings.
|
||||
This setting takes place when output is enabled.
|
||||
**/
|
||||
UINT32 OutputState : 2;
|
||||
/**
|
||||
GPIO Interrupt Configuration
|
||||
Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI).
|
||||
This setting is applicable only if GPIO is in GpioMode with input enabled.
|
||||
Refer to definition of GPIO_INT_CONFIG for supported settings.
|
||||
**/
|
||||
UINT32 InterruptConfig : 9;
|
||||
/**
|
||||
GPIO Power Configuration.
|
||||
This setting controls Pad Reset Configuration.
|
||||
Refer to definition of GPIO_RESET_CONFIG for supported settings.
|
||||
**/
|
||||
UINT32 PowerConfig : 8;
|
||||
/**
|
||||
GPIO Electrical Configuration
|
||||
This setting controls pads termination and voltage tolerance.
|
||||
Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings.
|
||||
**/
|
||||
UINT32 ElectricalConfig : 9;
|
||||
/**
|
||||
GPIO Lock Configuration
|
||||
This setting controls pads lock.
|
||||
Refer to definition of GPIO_LOCK_CONFIG for supported settings.
|
||||
**/
|
||||
UINT32 LockConfig : 4;
|
||||
/**
|
||||
Additional GPIO configuration
|
||||
Refer to definition of GPIO_OTHER_CONFIG for supported settings.
|
||||
**/
|
||||
UINT32 OtherSettings : 2;
|
||||
UINT32 RsvdBits : 17; ///< Reserved bits for future extension
|
||||
} GPIO_CONFIG;
|
||||
|
||||
|
||||
typedef enum {
|
||||
GpioHardwareDefault = 0x0 ///< Leave setting unmodified
|
||||
} GPIO_HARDWARE_DEFAULT;
|
||||
|
||||
/**
|
||||
GPIO Pad Mode
|
||||
Refer to GPIO documentation on native functions available for certain pad.
|
||||
If GPIO is set to one of NativeX modes then following settings are not applicable
|
||||
and can be skipped:
|
||||
- Interrupt related settings
|
||||
- Host Software Ownership
|
||||
- Output/Input enabling/disabling
|
||||
- Output lock
|
||||
**/
|
||||
typedef enum {
|
||||
GpioPadModeGpio = 0x1,
|
||||
GpioPadModeNative1 = 0x3,
|
||||
GpioPadModeNative2 = 0x5,
|
||||
GpioPadModeNative3 = 0x7,
|
||||
GpioPadModeNative4 = 0x9
|
||||
} GPIO_PAD_MODE;
|
||||
|
||||
/**
|
||||
Host Software Pad Ownership modes
|
||||
This setting affects GPIO interrupt status registers. Depending on chosen ownership
|
||||
some GPIO Interrupt status register get updated and other masked.
|
||||
Please refer to EDS for HOSTSW_OWN register description.
|
||||
**/
|
||||
typedef enum {
|
||||
GpioHostOwnDefault = 0x0, ///< Leave ownership value unmodified
|
||||
/**
|
||||
Set HOST ownership to ACPI.
|
||||
Use this setting if pad is not going to be used by GPIO OS driver.
|
||||
If GPIO is configured to generate SCI/SMI/NMI then this setting must be
|
||||
used for interrupts to work
|
||||
**/
|
||||
GpioHostOwnAcpi = 0x1,
|
||||
/**
|
||||
Set HOST ownership to GPIO Driver mode.
|
||||
Use this setting only if GPIO pad should be controlled by GPIO OS Driver.
|
||||
GPIO OS Driver will be able to control the pad if appropriate entry in
|
||||
ACPI exists (refer to ACPI specification for GpioIo and GpioInt descriptors)
|
||||
**/
|
||||
GpioHostOwnGpio = 0x3
|
||||
} GPIO_HOSTSW_OWN;
|
||||
|
||||
///
|
||||
/// GPIO Direction
|
||||
///
|
||||
typedef enum {
|
||||
GpioDirDefault = 0x0, ///< Leave pad direction setting unmodified
|
||||
GpioDirInOut = (0x1 | (0x1 << 3)), ///< Set pad for both output and input
|
||||
GpioDirInInvOut = (0x1 | (0x3 << 3)), ///< Set pad for both output and input with inversion
|
||||
GpioDirIn = (0x3 | (0x1 << 3)), ///< Set pad for input only
|
||||
GpioDirInInv = (0x3 | (0x3 << 3)), ///< Set pad for input with inversion
|
||||
GpioDirOut = 0x5, ///< Set pad for output only
|
||||
GpioDirNone = 0x7 ///< Disable both output and input
|
||||
} GPIO_DIRECTION;
|
||||
|
||||
/**
|
||||
GPIO Output State
|
||||
This field is relevant only if output is enabled
|
||||
**/
|
||||
typedef enum {
|
||||
GpioOutDefault = 0x0, ///< Leave output value unmodified
|
||||
GpioOutLow = 0x1, ///< Set output to low
|
||||
GpioOutHigh = 0x3 ///< Set output to high
|
||||
} GPIO_OUTPUT_STATE;
|
||||
|
||||
/**
|
||||
GPIO interrupt configuration
|
||||
This setting is applicable only if pad is in GPIO mode and has input enabled.
|
||||
GPIO_INT_CONFIG allows to choose which interrupt is generated (IOxAPIC/SCI/SMI/NMI)
|
||||
and how it is triggered (edge or level). Refer to PADCFG_DW0 register description in
|
||||
EDS for details on this settings.
|
||||
Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to GpioIntBothEdge
|
||||
to describe an interrupt e.g. GpioIntApic | GpioIntLevel
|
||||
If GPIO is set to cause an SCI then also GPI_GPE_EN is enabled for this pad.
|
||||
If GPIO is set to cause an NMI then also GPI_NMI_EN is enabled for this pad.
|
||||
Not all GPIO are capable of generating an SMI or NMI interrupt.
|
||||
When routing GPIO to cause an IOxAPIC interrupt care must be taken, as this
|
||||
interrupt cannot be shared and its IRQn number is not configurable.
|
||||
Refer to EDS for GPIO pads IRQ numbers (PADCFG_DW1.IntSel)
|
||||
If GPIO is under GPIO OS driver control and appropriate ACPI GpioInt descriptor
|
||||
exist then use only trigger type setting (from GpioIntLevel to GpioIntBothEdge).
|
||||
This type of GPIO Driver interrupt doesn't have any additional routing setting
|
||||
required to be set by BIOS. Interrupt is handled by GPIO OS Driver.
|
||||
**/
|
||||
|
||||
typedef enum {
|
||||
GpioIntDefault = 0x0, ///< Leave value of interrupt routing unmodified
|
||||
GpioIntDis = 0x1, ///< Disable IOxAPIC/SCI/SMI/NMI interrupt generation
|
||||
GpioIntNmi = 0x3, ///< Enable NMI interrupt only
|
||||
GpioIntSmi = 0x5, ///< Enable SMI interrupt only
|
||||
GpioIntSci = 0x9, ///< Enable SCI interrupt only
|
||||
GpioIntApic = 0x11, ///< Enable IOxAPIC interrupt only
|
||||
GpioIntLevel = (0x1 << 5), ///< Set interrupt as level triggered
|
||||
GpioIntEdge = (0x3 << 5), ///< Set interrupt as edge triggered (type of edge depends on input inversion)
|
||||
GpioIntLvlEdgDis = (0x5 << 5), ///< Disable interrupt trigger
|
||||
GpioIntBothEdge = (0x7 << 5) ///< Set interrupt as both edge triggered
|
||||
} GPIO_INT_CONFIG;
|
||||
|
||||
#define B_GPIO_INT_CONFIG_INT_SOURCE_MASK 0x1F ///< Mask for GPIO_INT_CONFIG for interrupt source
|
||||
#define B_GPIO_INT_CONFIG_INT_TYPE_MASK 0xE0 ///< Mask for GPIO_INT_CONFIG for interrupt type
|
||||
|
||||
/**
|
||||
GPIO Power Configuration
|
||||
GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0.PadRstCfg) which will
|
||||
be used to reset certain GPIO settings.
|
||||
Refer to EDS for settings that are controllable by PadRstCfg.
|
||||
**/
|
||||
typedef enum {
|
||||
|
||||
|
||||
GpioResetDefault = 0x00, ///< Leave value of pad reset unmodified
|
||||
|
||||
///
|
||||
/// New GPIO reset configuration options
|
||||
///
|
||||
/**
|
||||
Resume Reset (RSMRST)
|
||||
GPP: PadRstCfg = 00b = "Powergood"
|
||||
GPD: PadRstCfg = 11b = "Resume Reset"
|
||||
Pad setting will reset on:
|
||||
- DeepSx transition
|
||||
- G3
|
||||
Pad settings will not reset on:
|
||||
- S3/S4/S5 transition
|
||||
- Warm/Cold/Global reset
|
||||
**/
|
||||
GpioResumeReset = 0x01,
|
||||
/**
|
||||
Host Deep Reset
|
||||
PadRstCfg = 01b = "Deep GPIO Reset"
|
||||
Pad settings will reset on:
|
||||
- Warm/Cold/Global reset
|
||||
- DeepSx transition
|
||||
- G3
|
||||
Pad settings will not reset on:
|
||||
- S3/S4/S5 transition
|
||||
**/
|
||||
GpioHostDeepReset = 0x03,
|
||||
/**
|
||||
Platform Reset (PLTRST)
|
||||
PadRstCfg = 10b = "GPIO Reset"
|
||||
Pad settings will reset on:
|
||||
- S3/S4/S5 transition
|
||||
- Warm/Cold/Global reset
|
||||
- DeepSx transition
|
||||
- G3
|
||||
**/
|
||||
GpioPlatformReset = 0x05,
|
||||
/**
|
||||
Deep Sleep Well Reset (DSW_PWROK)
|
||||
GPP: not applicable
|
||||
GPD: PadRstCfg = 00b = "Powergood"
|
||||
Pad settings will reset on:
|
||||
- G3
|
||||
Pad settings will not reset on:
|
||||
- S3/S4/S5 transition
|
||||
- Warm/Cold/Global reset
|
||||
- DeepSx transition
|
||||
**/
|
||||
GpioDswReset = 0x07
|
||||
} GPIO_RESET_CONFIG;
|
||||
|
||||
/**
|
||||
GPIO Electrical Configuration
|
||||
Set GPIO termination and Pad Tolerance (applicable only for some pads)
|
||||
Field from GpioTermNone to GpioTermNative can be OR'ed with GpioTolerance1v8.
|
||||
**/
|
||||
typedef enum {
|
||||
GpioTermDefault = 0x0, ///< Leave termination setting unmodified
|
||||
GpioTermNone = 0x1, ///< none
|
||||
GpioTermWpd5K = 0x5, ///< 5kOhm weak pull-down
|
||||
GpioTermWpd20K = 0x9, ///< 20kOhm weak pull-down
|
||||
GpioTermWpu1K = 0x13, ///< 1kOhm weak pull-up
|
||||
GpioTermWpu2K = 0x17, ///< 2kOhm weak pull-up
|
||||
GpioTermWpu5K = 0x15, ///< 5kOhm weak pull-up
|
||||
GpioTermWpu20K = 0x19, ///< 20kOhm weak pull-up
|
||||
GpioTermWpu1K2K = 0x1B, ///< 1kOhm & 2kOhm weak pull-up
|
||||
/**
|
||||
Native function controls pads termination
|
||||
This setting is applicable only to some native modes.
|
||||
Please check EDS to determine which native functionality
|
||||
can control pads termination
|
||||
**/
|
||||
GpioTermNative = 0x1F,
|
||||
GpioNoTolerance1v8 = (0x1 << 5), ///< Disable 1.8V pad tolerance
|
||||
GpioTolerance1v8 = (0x3 << 5) ///< Enable 1.8V pad tolerance
|
||||
} GPIO_ELECTRICAL_CONFIG;
|
||||
|
||||
#define B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK 0x1F ///< Mask for GPIO_ELECTRICAL_CONFIG for termination value
|
||||
#define B_GPIO_ELECTRICAL_CONFIG_1V8_TOLERANCE_MASK 0x60 ///< Mask for GPIO_ELECTRICAL_CONFIG for 1v8 tolerance setting
|
||||
|
||||
/**
|
||||
GPIO LockConfiguration
|
||||
Set GPIO configuration lock and output state lock.
|
||||
GpioLockPadConfig and GpioLockOutputState can be OR'ed.
|
||||
Lock settings reset is in Powergood domain. Care must be taken when using this setting
|
||||
as fields it locks may be reset by a different signal and can be controllable
|
||||
by what is in GPIO_RESET_CONFIG (PADCFG_DW0.PadRstCfg). GPIO library provides
|
||||
functions which allow to unlock a GPIO pad.
|
||||
**/
|
||||
typedef enum {
|
||||
GpioLockDefault = 0x0, ///< Leave lock setting unmodified
|
||||
GpioPadConfigLock = 0x3, ///< Lock Pad Configuration
|
||||
GpioOutputStateLock = 0x5 ///< Lock GPIO pad output value
|
||||
} GPIO_LOCK_CONFIG;
|
||||
|
||||
#define B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK 0x3 ///< Mask for GPIO_LOCK_CONFIG for Pad Configuration Lock
|
||||
#define B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK 0x5 ///< Mask for GPIO_LOCK_CONFIG for Pad Output Lock
|
||||
|
||||
/**
|
||||
Other GPIO Configuration
|
||||
GPIO_OTHER_CONFIG is used for less often settings and for future extensions
|
||||
Supported settings:
|
||||
- RX raw override to '1' - allows to override input value to '1'
|
||||
This setting is applicable only if in input mode (both in GPIO and native usage).
|
||||
The override takes place at the internal pad state directly from buffer and before the RXINV.
|
||||
**/
|
||||
typedef enum {
|
||||
GpioRxRaw1Default = 0x0, ///< Use default input override value
|
||||
GpioRxRaw1Dis = 0x1, ///< Don't override input
|
||||
GpioRxRaw1En = 0x3 ///< Override input to '1'
|
||||
} GPIO_OTHER_CONFIG;
|
||||
|
||||
#define B_GPIO_OTHER_CONFIG_RXRAW_MASK 0x3 ///< Mask for GPIO_OTHER_CONFIG for RxRaw1 setting
|
||||
|
||||
#pragma pack(pop)
|
||||
|
||||
#endif //_GPIO_CONFIG_H_
|
||||
382
models/lemp13/MeteorLakeFspBinPkg/Include/GpioSampleDef.h
Normal file
382
models/lemp13/MeteorLakeFspBinPkg/Include/GpioSampleDef.h
Normal file
@ -0,0 +1,382 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
* Redistributions in binary form must reproduce the above copyright notice, this
|
||||
list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
|
||||
* Neither the name of Intel Corporation nor the names of its contributors may
|
||||
be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
This file is automatically generated. Please do NOT modify !!!
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __GPIOCONFIG_H__
|
||||
#define __GPIOCONFIG_H__
|
||||
#include <FsptUpd.h>
|
||||
#include <FspmUpd.h>
|
||||
#include <FspsUpd.h>
|
||||
|
||||
/*
|
||||
SKL LP GPIO pins
|
||||
Use below for functions from PCH GPIO Lib which
|
||||
require GpioPad as argument. Encoding used here
|
||||
has all information required by library functions
|
||||
*/
|
||||
#define GPIO_SKL_LP_GPP_A0 0x02000000
|
||||
#define GPIO_SKL_LP_GPP_A1 0x02000001
|
||||
#define GPIO_SKL_LP_GPP_A2 0x02000002
|
||||
#define GPIO_SKL_LP_GPP_A3 0x02000003
|
||||
#define GPIO_SKL_LP_GPP_A4 0x02000004
|
||||
#define GPIO_SKL_LP_GPP_A5 0x02000005
|
||||
#define GPIO_SKL_LP_GPP_A6 0x02000006
|
||||
#define GPIO_SKL_LP_GPP_A7 0x02000007
|
||||
#define GPIO_SKL_LP_GPP_A8 0x02000008
|
||||
#define GPIO_SKL_LP_GPP_A9 0x02000009
|
||||
#define GPIO_SKL_LP_GPP_A10 0x0200000A
|
||||
#define GPIO_SKL_LP_GPP_A11 0x0200000B
|
||||
#define GPIO_SKL_LP_GPP_A12 0x0200000C
|
||||
#define GPIO_SKL_LP_GPP_A13 0x0200000D
|
||||
#define GPIO_SKL_LP_GPP_A14 0x0200000E
|
||||
#define GPIO_SKL_LP_GPP_A15 0x0200000F
|
||||
#define GPIO_SKL_LP_GPP_A16 0x02000010
|
||||
#define GPIO_SKL_LP_GPP_A17 0x02000011
|
||||
#define GPIO_SKL_LP_GPP_A18 0x02000012
|
||||
#define GPIO_SKL_LP_GPP_A19 0x02000013
|
||||
#define GPIO_SKL_LP_GPP_A20 0x02000014
|
||||
#define GPIO_SKL_LP_GPP_A21 0x02000015
|
||||
#define GPIO_SKL_LP_GPP_A22 0x02000016
|
||||
#define GPIO_SKL_LP_GPP_A23 0x02000017
|
||||
#define GPIO_SKL_LP_GPP_B0 0x02010000
|
||||
#define GPIO_SKL_LP_GPP_B1 0x02010001
|
||||
#define GPIO_SKL_LP_GPP_B2 0x02010002
|
||||
#define GPIO_SKL_LP_GPP_B3 0x02010003
|
||||
#define GPIO_SKL_LP_GPP_B4 0x02010004
|
||||
#define GPIO_SKL_LP_GPP_B5 0x02010005
|
||||
#define GPIO_SKL_LP_GPP_B6 0x02010006
|
||||
#define GPIO_SKL_LP_GPP_B7 0x02010007
|
||||
#define GPIO_SKL_LP_GPP_B8 0x02010008
|
||||
#define GPIO_SKL_LP_GPP_B9 0x02010009
|
||||
#define GPIO_SKL_LP_GPP_B10 0x0201000A
|
||||
#define GPIO_SKL_LP_GPP_B11 0x0201000B
|
||||
#define GPIO_SKL_LP_GPP_B12 0x0201000C
|
||||
#define GPIO_SKL_LP_GPP_B13 0x0201000D
|
||||
#define GPIO_SKL_LP_GPP_B14 0x0201000E
|
||||
#define GPIO_SKL_LP_GPP_B15 0x0201000F
|
||||
#define GPIO_SKL_LP_GPP_B16 0x02010010
|
||||
#define GPIO_SKL_LP_GPP_B17 0x02010011
|
||||
#define GPIO_SKL_LP_GPP_B18 0x02010012
|
||||
#define GPIO_SKL_LP_GPP_B19 0x02010013
|
||||
#define GPIO_SKL_LP_GPP_B20 0x02010014
|
||||
#define GPIO_SKL_LP_GPP_B21 0x02010015
|
||||
#define GPIO_SKL_LP_GPP_B22 0x02010016
|
||||
#define GPIO_SKL_LP_GPP_B23 0x02010017
|
||||
#define GPIO_SKL_LP_GPP_C0 0x02020000
|
||||
#define GPIO_SKL_LP_GPP_C1 0x02020001
|
||||
#define GPIO_SKL_LP_GPP_C2 0x02020002
|
||||
#define GPIO_SKL_LP_GPP_C3 0x02020003
|
||||
#define GPIO_SKL_LP_GPP_C4 0x02020004
|
||||
#define GPIO_SKL_LP_GPP_C5 0x02020005
|
||||
#define GPIO_SKL_LP_GPP_C6 0x02020006
|
||||
#define GPIO_SKL_LP_GPP_C7 0x02020007
|
||||
#define GPIO_SKL_LP_GPP_C8 0x02020008
|
||||
#define GPIO_SKL_LP_GPP_C9 0x02020009
|
||||
#define GPIO_SKL_LP_GPP_C10 0x0202000A
|
||||
#define GPIO_SKL_LP_GPP_C11 0x0202000B
|
||||
#define GPIO_SKL_LP_GPP_C12 0x0202000C
|
||||
#define GPIO_SKL_LP_GPP_C13 0x0202000D
|
||||
#define GPIO_SKL_LP_GPP_C14 0x0202000E
|
||||
#define GPIO_SKL_LP_GPP_C15 0x0202000F
|
||||
#define GPIO_SKL_LP_GPP_C16 0x02020010
|
||||
#define GPIO_SKL_LP_GPP_C17 0x02020011
|
||||
#define GPIO_SKL_LP_GPP_C18 0x02020012
|
||||
#define GPIO_SKL_LP_GPP_C19 0x02020013
|
||||
#define GPIO_SKL_LP_GPP_C20 0x02020014
|
||||
#define GPIO_SKL_LP_GPP_C21 0x02020015
|
||||
#define GPIO_SKL_LP_GPP_C22 0x02020016
|
||||
#define GPIO_SKL_LP_GPP_C23 0x02020017
|
||||
#define GPIO_SKL_LP_GPP_D0 0x02030000
|
||||
#define GPIO_SKL_LP_GPP_D1 0x02030001
|
||||
#define GPIO_SKL_LP_GPP_D2 0x02030002
|
||||
#define GPIO_SKL_LP_GPP_D3 0x02030003
|
||||
#define GPIO_SKL_LP_GPP_D4 0x02030004
|
||||
#define GPIO_SKL_LP_GPP_D5 0x02030005
|
||||
#define GPIO_SKL_LP_GPP_D6 0x02030006
|
||||
#define GPIO_SKL_LP_GPP_D7 0x02030007
|
||||
#define GPIO_SKL_LP_GPP_D8 0x02030008
|
||||
#define GPIO_SKL_LP_GPP_D9 0x02030009
|
||||
#define GPIO_SKL_LP_GPP_D10 0x0203000A
|
||||
#define GPIO_SKL_LP_GPP_D11 0x0203000B
|
||||
#define GPIO_SKL_LP_GPP_D12 0x0203000C
|
||||
#define GPIO_SKL_LP_GPP_D13 0x0203000D
|
||||
#define GPIO_SKL_LP_GPP_D14 0x0203000E
|
||||
#define GPIO_SKL_LP_GPP_D15 0x0203000F
|
||||
#define GPIO_SKL_LP_GPP_D16 0x02030010
|
||||
#define GPIO_SKL_LP_GPP_D17 0x02030011
|
||||
#define GPIO_SKL_LP_GPP_D18 0x02030012
|
||||
#define GPIO_SKL_LP_GPP_D19 0x02030013
|
||||
#define GPIO_SKL_LP_GPP_D20 0x02030014
|
||||
#define GPIO_SKL_LP_GPP_D21 0x02030015
|
||||
#define GPIO_SKL_LP_GPP_D22 0x02030016
|
||||
#define GPIO_SKL_LP_GPP_D23 0x02030017
|
||||
#define GPIO_SKL_LP_GPP_E0 0x02040000
|
||||
#define GPIO_SKL_LP_GPP_E1 0x02040001
|
||||
#define GPIO_SKL_LP_GPP_E2 0x02040002
|
||||
#define GPIO_SKL_LP_GPP_E3 0x02040003
|
||||
#define GPIO_SKL_LP_GPP_E4 0x02040004
|
||||
#define GPIO_SKL_LP_GPP_E5 0x02040005
|
||||
#define GPIO_SKL_LP_GPP_E6 0x02040006
|
||||
#define GPIO_SKL_LP_GPP_E7 0x02040007
|
||||
#define GPIO_SKL_LP_GPP_E8 0x02040008
|
||||
#define GPIO_SKL_LP_GPP_E9 0x02040009
|
||||
#define GPIO_SKL_LP_GPP_E10 0x0204000A
|
||||
#define GPIO_SKL_LP_GPP_E11 0x0204000B
|
||||
#define GPIO_SKL_LP_GPP_E12 0x0204000C
|
||||
#define GPIO_SKL_LP_GPP_E13 0x0204000D
|
||||
#define GPIO_SKL_LP_GPP_E14 0x0204000E
|
||||
#define GPIO_SKL_LP_GPP_E15 0x0204000F
|
||||
#define GPIO_SKL_LP_GPP_E16 0x02040010
|
||||
#define GPIO_SKL_LP_GPP_E17 0x02040011
|
||||
#define GPIO_SKL_LP_GPP_E18 0x02040012
|
||||
#define GPIO_SKL_LP_GPP_E19 0x02040013
|
||||
#define GPIO_SKL_LP_GPP_E20 0x02040014
|
||||
#define GPIO_SKL_LP_GPP_E21 0x02040015
|
||||
#define GPIO_SKL_LP_GPP_E22 0x02040016
|
||||
#define GPIO_SKL_LP_GPP_E23 0x02040017
|
||||
#define GPIO_SKL_LP_GPP_F0 0x02050000
|
||||
#define GPIO_SKL_LP_GPP_F1 0x02050001
|
||||
#define GPIO_SKL_LP_GPP_F2 0x02050002
|
||||
#define GPIO_SKL_LP_GPP_F3 0x02050003
|
||||
#define GPIO_SKL_LP_GPP_F4 0x02050004
|
||||
#define GPIO_SKL_LP_GPP_F5 0x02050005
|
||||
#define GPIO_SKL_LP_GPP_F6 0x02050006
|
||||
#define GPIO_SKL_LP_GPP_F7 0x02050007
|
||||
#define GPIO_SKL_LP_GPP_F8 0x02050008
|
||||
#define GPIO_SKL_LP_GPP_F9 0x02050009
|
||||
#define GPIO_SKL_LP_GPP_F10 0x0205000A
|
||||
#define GPIO_SKL_LP_GPP_F11 0x0205000B
|
||||
#define GPIO_SKL_LP_GPP_F12 0x0205000C
|
||||
#define GPIO_SKL_LP_GPP_F13 0x0205000D
|
||||
#define GPIO_SKL_LP_GPP_F14 0x0205000E
|
||||
#define GPIO_SKL_LP_GPP_F15 0x0205000F
|
||||
#define GPIO_SKL_LP_GPP_F16 0x02050010
|
||||
#define GPIO_SKL_LP_GPP_F17 0x02050011
|
||||
#define GPIO_SKL_LP_GPP_F18 0x02050012
|
||||
#define GPIO_SKL_LP_GPP_F19 0x02050013
|
||||
#define GPIO_SKL_LP_GPP_F20 0x02050014
|
||||
#define GPIO_SKL_LP_GPP_F21 0x02050015
|
||||
#define GPIO_SKL_LP_GPP_F22 0x02050016
|
||||
#define GPIO_SKL_LP_GPP_F23 0x02050017
|
||||
#define GPIO_SKL_LP_GPP_G0 0x02060000
|
||||
#define GPIO_SKL_LP_GPP_G1 0x02060001
|
||||
#define GPIO_SKL_LP_GPP_G2 0x02060002
|
||||
#define GPIO_SKL_LP_GPP_G3 0x02060003
|
||||
#define GPIO_SKL_LP_GPP_G4 0x02060004
|
||||
#define GPIO_SKL_LP_GPP_G5 0x02060005
|
||||
#define GPIO_SKL_LP_GPP_G6 0x02060006
|
||||
#define GPIO_SKL_LP_GPP_G7 0x02060007
|
||||
#define GPIO_SKL_LP_GPD0 0x02070000
|
||||
#define GPIO_SKL_LP_GPD1 0x02070001
|
||||
#define GPIO_SKL_LP_GPD2 0x02070002
|
||||
#define GPIO_SKL_LP_GPD3 0x02070003
|
||||
#define GPIO_SKL_LP_GPD4 0x02070004
|
||||
#define GPIO_SKL_LP_GPD5 0x02070005
|
||||
#define GPIO_SKL_LP_GPD6 0x02070006
|
||||
#define GPIO_SKL_LP_GPD7 0x02070007
|
||||
#define GPIO_SKL_LP_GPD8 0x02070008
|
||||
#define GPIO_SKL_LP_GPD9 0x02070009
|
||||
#define GPIO_SKL_LP_GPD10 0x0207000A
|
||||
#define GPIO_SKL_LP_GPD11 0x0207000B
|
||||
|
||||
#define END_OF_GPIO_TABLE 0xFFFFFFFF
|
||||
|
||||
//Sample GPIO Table
|
||||
|
||||
static GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3[] =
|
||||
{
|
||||
//skip for eSPI function {GPIO_SKL_LP_GPP_A0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//H_RCIN_N
|
||||
//skip for eSPI function {GPIO_SKL_LP_GPP_A1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD0_ESPI_IO0
|
||||
//skip for eSPI function {GPIO_SKL_LP_GPP_A2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD1_ESPI_IO1
|
||||
//skip for eSPI function {GPIO_SKL_LP_GPP_A3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD2_ESPI_IO2
|
||||
//skip for eSPI function {GPIO_SKL_LP_GPP_A4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD3_ESPI_IO3
|
||||
//skip for eSPI function {GPIO_SKL_LP_GPP_A5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//LPC_FRAME_ESPI_CS_N
|
||||
//skip for eSPI function {GPIO_SKL_LP_GPP_A6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//INT_SERIRQ
|
||||
//skip for eSPI function {GPIO_SKL_LP_GPP_A7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_SLP_S0ix_R_N
|
||||
{GPIO_SKL_LP_GPP_A8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_CLKRUN_N
|
||||
//skip for eSPI function {GPIO_SKL_LP_GPP_A9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_CLK_ESPI_CLK
|
||||
{GPIO_SKL_LP_GPP_A10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//PCH_CLK_PCI_TPM
|
||||
{GPIO_SKL_LP_GPP_A11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//EC_HID_INTR
|
||||
{GPIO_SKL_LP_GPP_A12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//M.2_WWAN_GNSS_UART_RST_N
|
||||
{GPIO_SKL_LP_GPP_A13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SUS_PWR_ACK_R
|
||||
//skip for eSPI function {GPIO_SKL_LP_GPP_A14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_SUS_STAT_ESPI_RST_N
|
||||
{GPIO_SKL_LP_GPP_A15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SUSACK_R_N
|
||||
{GPIO_SKL_LP_GPP_A16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_1P8_SEL
|
||||
{GPIO_SKL_LP_GPP_A17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_PWR_EN_N
|
||||
{GPIO_SKL_LP_GPP_A18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_0_SENSOR
|
||||
{GPIO_SKL_LP_GPP_A19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_1_SENSOR
|
||||
{GPIO_SKL_LP_GPP_A20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_2_SENSOR
|
||||
{GPIO_SKL_LP_GPP_A21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//GNSS_CHUB_IRQ
|
||||
{GPIO_SKL_LP_GPP_A22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//FPS_SLP_N
|
||||
{GPIO_SKL_LP_GPP_A23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//FPS_DRDY
|
||||
{GPIO_SKL_LP_GPP_B0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//V0.85A_VID0
|
||||
{GPIO_SKL_LP_GPP_B1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//V0.85A_VID1
|
||||
{GPIO_SKL_LP_GPP_B2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//GP_VRALERTB
|
||||
{GPIO_SKL_LP_GPP_B3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTermNone}},//TCH_PAD_INTR_R_N
|
||||
{GPIO_SKL_LP_GPP_B4, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//BT_RF_KILL_N
|
||||
{GPIO_SKL_LP_GPP_B5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//M.2_BT_UART_WAKE_N
|
||||
// {GPIO_SKL_LP_GPP_B6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_SLOT1_N
|
||||
// {GPIO_SKL_LP_GPP_B7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_SLOT2_LAN_N
|
||||
// {GPIO_SKL_LP_GPP_B8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_SSD_SLOT3_N
|
||||
// {GPIO_SKL_LP_GPP_B9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_WIGIG_N
|
||||
// {GPIO_SKL_LP_GPP_B10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_WLAN_N
|
||||
{GPIO_SKL_LP_GPP_B11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//MPHY_EXT_PWR_GATEB
|
||||
{GPIO_SKL_LP_GPP_B12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_SLP_S0_N
|
||||
{GPIO_SKL_LP_GPP_B13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PLT_RST_N
|
||||
{GPIO_SKL_LP_GPP_B14, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//TCH_PNL_PWREN
|
||||
{GPIO_SKL_LP_GPP_B15, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_DFU
|
||||
{GPIO_SKL_LP_GPP_B16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermNone}},//M.2_WLAN_WIFI_WAKE_N
|
||||
{GPIO_SKL_LP_GPP_B17, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSci, GpioHostDeepReset, GpioTermWpd20K}},//TBT_CIO_PLUG_EVENT_N
|
||||
{GPIO_SKL_LP_GPP_B18, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermWpu20K}},//PCH_SLOT1_WAKE_N
|
||||
{GPIO_SKL_LP_GPP_B19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//FPS_GSPI1_CS_R1_N
|
||||
{GPIO_SKL_LP_GPP_B20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_CLK_R1
|
||||
{GPIO_SKL_LP_GPP_B21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_MISO_R1
|
||||
{GPIO_SKL_LP_GPP_B22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_MOSI_R1
|
||||
{GPIO_SKL_LP_GPP_B23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DISCRETE_GNSS_RESET_N
|
||||
{GPIO_SKL_LP_GPP_C0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SMB_CLK
|
||||
{GPIO_SKL_LP_GPP_C1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SMB_DATA
|
||||
{GPIO_SKL_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SKIN_THRM_SNSR_ALERT_N
|
||||
{GPIO_SKL_LP_GPP_C3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML0_CLK
|
||||
{GPIO_SKL_LP_GPP_C4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML0_DATA
|
||||
{GPIO_SKL_LP_GPP_C5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermWpd20K}},//M.2_WIGIG_WAKE_N
|
||||
{GPIO_SKL_LP_GPP_C6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML1_CLK
|
||||
{GPIO_SKL_LP_GPP_C7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SML1_DATA
|
||||
{GPIO_SKL_LP_GPP_C8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_RXD
|
||||
{GPIO_SKL_LP_GPP_C9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_TXD
|
||||
{GPIO_SKL_LP_GPP_C10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_RTS_N
|
||||
{GPIO_SKL_LP_GPP_C11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_CTS_N
|
||||
{GPIO_SKL_LP_GPP_C12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RXD
|
||||
{GPIO_SKL_LP_GPP_C13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_TXD
|
||||
{GPIO_SKL_LP_GPP_C14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RTS_N
|
||||
{GPIO_SKL_LP_GPP_C15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_CTS_N
|
||||
{GPIO_SKL_LP_GPP_C16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C0_SDA
|
||||
{GPIO_SKL_LP_GPP_C17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C0_SCL
|
||||
{GPIO_SKL_LP_GPP_C18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C1_SDA
|
||||
{GPIO_SKL_LP_GPP_C19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C1_SCL
|
||||
{GPIO_SKL_LP_GPP_C20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_RXD
|
||||
{GPIO_SKL_LP_GPP_C21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_TXD
|
||||
{GPIO_SKL_LP_GPP_C22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_RTS_N
|
||||
{GPIO_SKL_LP_GPP_C23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_CTS_N
|
||||
{GPIO_SKL_LP_GPP_D0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_CS_N
|
||||
{GPIO_SKL_LP_GPP_D1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_CLK
|
||||
{GPIO_SKL_LP_GPP_D2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_MISO
|
||||
{GPIO_SKL_LP_GPP_D3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_MOSI
|
||||
{GPIO_SKL_LP_GPP_D4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CSI2_FLASH_STROBE
|
||||
{GPIO_SKL_LP_GPP_D5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C0_SDA
|
||||
{GPIO_SKL_LP_GPP_D6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C0_SCL
|
||||
{GPIO_SKL_LP_GPP_D7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C1_SDA
|
||||
{GPIO_SKL_LP_GPP_D8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C1_SCL
|
||||
{GPIO_SKL_LP_GPP_D9, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//HOME_BTN
|
||||
{GPIO_SKL_LP_GPP_D10, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SCREEN_LOCK_PCH
|
||||
{GPIO_SKL_LP_GPP_D11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//VOL_UP_PCH
|
||||
{GPIO_SKL_LP_GPP_D12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//VOL_DOWN_PCH
|
||||
{GPIO_SKL_LP_GPP_D13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_RXD_SML0B_DATA
|
||||
{GPIO_SKL_LP_GPP_D14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_TXD_SML0B_CLK
|
||||
{GPIO_SKL_LP_GPP_D15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_RTS_N
|
||||
{GPIO_SKL_LP_GPP_D16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_CTS_SML0B_ALERT_N
|
||||
{GPIO_SKL_LP_GPP_D17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_CLK_1
|
||||
{GPIO_SKL_LP_GPP_D18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_DATA_1
|
||||
{GPIO_SKL_LP_GPP_D19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_CLK_0
|
||||
{GPIO_SKL_LP_GPP_D20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_DATA_0
|
||||
{GPIO_SKL_LP_GPP_D21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_IO2
|
||||
{GPIO_SKL_LP_GPP_D22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_IO3
|
||||
{GPIO_SKL_LP_GPP_D23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP_MCLK
|
||||
{GPIO_SKL_LP_GPP_E0, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//SPI_TPM_HDR_IRQ_N
|
||||
{GPIO_SKL_LP_GPP_E1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA_ODD_PRSNT_N
|
||||
{GPIO_SKL_LP_GPP_E2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntLvlEdgDis | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//M.2_SSD_SATA2_PCIE3_DET_N
|
||||
{GPIO_SKL_LP_GPP_E3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone}},//EINK_SSR_DFU_N
|
||||
{GPIO_SKL_LP_GPP_E4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_RESET
|
||||
{GPIO_SKL_LP_GPP_E5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA1_PHYSLP1_DIRECT_R
|
||||
{GPIO_SKL_LP_GPP_E6, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA2_PHYSLP2_M.2SSD_R
|
||||
{GPIO_SKL_LP_GPP_E8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_SATA_LED_N
|
||||
{GPIO_SKL_LP_GPP_E9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_0_WP1_OTG_N
|
||||
{GPIO_SKL_LP_GPP_E10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_1_WP4_N
|
||||
{GPIO_SKL_LP_GPP_E11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_2_WP2_WP3_WP5_R_N
|
||||
{GPIO_SKL_LP_GPP_E12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_IRQ
|
||||
{GPIO_SKL_LP_GPP_E13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI1_HPD_Q
|
||||
{GPIO_SKL_LP_GPP_E14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI2_HPD_Q
|
||||
{GPIO_SKL_LP_GPP_E15, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSmi, GpioHostDeepReset, GpioTermNone}},//SMC_EXTSMI_R_N
|
||||
{GPIO_SKL_LP_GPP_E16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermNone}},//SMC_RUNTIME_SCI_R_N
|
||||
{GPIO_SKL_LP_GPP_E17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EDP_HPD
|
||||
{GPIO_SKL_LP_GPP_E18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI1_CTRL_CLK
|
||||
{GPIO_SKL_LP_GPP_E19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DDI1_CTRL_DATA
|
||||
{GPIO_SKL_LP_GPP_E20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI2_CTRL_CLK
|
||||
{GPIO_SKL_LP_GPP_E21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DDI2_CTRL_DATA
|
||||
{GPIO_SKL_LP_GPP_E22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//PCH_CODEC_IRQ
|
||||
{GPIO_SKL_LP_GPP_E23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//TCH_PNL_RST_N
|
||||
{GPIO_SKL_LP_GPP_F0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_SCLK
|
||||
{GPIO_SKL_LP_GPP_F1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_SFRM
|
||||
{GPIO_SKL_LP_GPP_F2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_TXD
|
||||
{GPIO_SKL_LP_GPP_F3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_RXD
|
||||
{GPIO_SKL_LP_GPP_F4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SDA
|
||||
{GPIO_SKL_LP_GPP_F5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SCL
|
||||
{GPIO_SKL_LP_GPP_F6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SDA
|
||||
{GPIO_SKL_LP_GPP_F7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SCL
|
||||
{GPIO_SKL_LP_GPP_F8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SDA
|
||||
{GPIO_SKL_LP_GPP_F9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SCL
|
||||
{GPIO_SKL_LP_GPP_F10, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SDA
|
||||
{GPIO_SKL_LP_GPP_F11, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SCL
|
||||
{GPIO_SKL_LP_GPP_F12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_CMD
|
||||
{GPIO_SKL_LP_GPP_F13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA0
|
||||
{GPIO_SKL_LP_GPP_F14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA1
|
||||
{GPIO_SKL_LP_GPP_F15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA2
|
||||
{GPIO_SKL_LP_GPP_F16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA3
|
||||
{GPIO_SKL_LP_GPP_F17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA4
|
||||
{GPIO_SKL_LP_GPP_F18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA5
|
||||
{GPIO_SKL_LP_GPP_F19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA6
|
||||
{GPIO_SKL_LP_GPP_F20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA7
|
||||
{GPIO_SKL_LP_GPP_F21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_RCLK
|
||||
{GPIO_SKL_LP_GPP_F22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_CLK
|
||||
{GPIO_SKL_LP_GPP_F23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//PCH_M.2_WWAN_UIM_SIM_DET
|
||||
{GPIO_SKL_LP_GPP_G0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CMD
|
||||
{GPIO_SKL_LP_GPP_G1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA0
|
||||
{GPIO_SKL_LP_GPP_G2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA1
|
||||
{GPIO_SKL_LP_GPP_G3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA2
|
||||
{GPIO_SKL_LP_GPP_G4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA3
|
||||
{GPIO_SKL_LP_GPP_G5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CDB
|
||||
{GPIO_SKL_LP_GPP_G6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CLK
|
||||
{GPIO_SKL_LP_GPP_G7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_WP
|
||||
{GPIO_SKL_LP_GPD0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PM_BATLOW_R_N
|
||||
{GPIO_SKL_LP_GPD1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//AC_PRESENT_R
|
||||
{GPIO_SKL_LP_GPD2, {GpioPadModeNative1, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioDswReset, GpioTermNone}},//LANWAKE_SMC_WAKE_SCI_N
|
||||
{GPIO_SKL_LP_GPD3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermWpu20K}},//PM_PWRBTN_R_N
|
||||
{GPIO_SKL_LP_GPD4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S3_R_N
|
||||
{GPIO_SKL_LP_GPD5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S4_R_N
|
||||
{GPIO_SKL_LP_GPD6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_M_R_N
|
||||
{GPIO_SKL_LP_GPD7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//USB_WAKEOUT_INTRUDET_N
|
||||
{GPIO_SKL_LP_GPD8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SUS_CLK
|
||||
{GPIO_SKL_LP_GPD9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PCH_SLP_WLAN_N
|
||||
{GPIO_SKL_LP_GPD10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S5_R_N
|
||||
{GPIO_SKL_LP_GPD11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PM_LANPHY_ENABLE
|
||||
{END_OF_GPIO_TABLE, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//Marking End of Table
|
||||
};
|
||||
|
||||
#endif //_GPIO_CONFIG_H_
|
||||
59
models/lemp13/MeteorLakeFspBinPkg/Include/HobUsageDataHob.h
Normal file
59
models/lemp13/MeteorLakeFspBinPkg/Include/HobUsageDataHob.h
Normal file
@ -0,0 +1,59 @@
|
||||
/** @file
|
||||
Definitions for Hob Usage data HOB
|
||||
|
||||
@copyright
|
||||
INTEL CONFIDENTIAL
|
||||
Copyright 2017 Intel Corporation.
|
||||
|
||||
The source code contained or described herein and all documents related to the
|
||||
source code ("Material") are owned by Intel Corporation or its suppliers or
|
||||
licensors. Title to the Material remains with Intel Corporation or its suppliers
|
||||
and licensors. The Material may contain trade secrets and proprietary and
|
||||
confidential information of Intel Corporation and its suppliers and licensors,
|
||||
and is protected by worldwide copyright and trade secret laws and treaty
|
||||
provisions. No part of the Material may be used, copied, reproduced, modified,
|
||||
published, uploaded, posted, transmitted, distributed, or disclosed in any way
|
||||
without Intel's prior express written permission.
|
||||
|
||||
No license under any patent, copyright, trade secret or other intellectual
|
||||
property right is granted to or conferred upon you by disclosure or delivery
|
||||
of the Materials, either expressly, by implication, inducement, estoppel or
|
||||
otherwise. Any license under such intellectual property rights must be
|
||||
express and approved by Intel in writing.
|
||||
|
||||
Unless otherwise agreed by Intel in writing, you may not remove or alter
|
||||
this notice or any other notice embedded in Materials by Intel or
|
||||
Intel's suppliers or licensors in any way.
|
||||
|
||||
This file contains an 'Intel Peripheral Driver' and is uniquely identified as
|
||||
"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
|
||||
the terms of your license agreement with Intel or your vendor. This file may
|
||||
be modified by the user, subject to additional terms of the license agreement.
|
||||
|
||||
@par Specification Reference:
|
||||
**/
|
||||
|
||||
#ifndef _HOB_USAGE_DATA_HOB_H_
|
||||
#define _HOB_USAGE_DATA_HOB_H_
|
||||
|
||||
extern EFI_GUID gHobUsageDataGuid;
|
||||
|
||||
#pragma pack (push, 1)
|
||||
|
||||
/**
|
||||
Hob Usage Data Hob
|
||||
|
||||
<b>Revision 1:</b>
|
||||
- Initial version.
|
||||
**/
|
||||
typedef struct {
|
||||
EFI_PHYSICAL_ADDRESS EfiMemoryTop;
|
||||
EFI_PHYSICAL_ADDRESS EfiMemoryBottom;
|
||||
EFI_PHYSICAL_ADDRESS EfiFreeMemoryTop;
|
||||
EFI_PHYSICAL_ADDRESS EfiFreeMemoryBottom;
|
||||
UINTN FreeMemory;
|
||||
} HOB_USAGE_DATA_HOB;
|
||||
|
||||
#pragma pack (pop)
|
||||
|
||||
#endif // _HOB_USAGE_DATA_HOB_H_
|
||||
344
models/lemp13/MeteorLakeFspBinPkg/Include/MemInfoHob.h
Normal file
344
models/lemp13/MeteorLakeFspBinPkg/Include/MemInfoHob.h
Normal file
@ -0,0 +1,344 @@
|
||||
/** @file
|
||||
This file contains definitions required for creation of
|
||||
Memory S3 Save data, Memory Info data and Memory Platform
|
||||
data hobs.
|
||||
|
||||
@copyright
|
||||
INTEL CONFIDENTIAL
|
||||
Copyright 1999 - 2022 Intel Corporation.
|
||||
|
||||
The source code contained or described herein and all documents related to the
|
||||
source code ("Material") are owned by Intel Corporation or its suppliers or
|
||||
licensors. Title to the Material remains with Intel Corporation or its suppliers
|
||||
and licensors. The Material may contain trade secrets and proprietary and
|
||||
confidential information of Intel Corporation and its suppliers and licensors,
|
||||
and is protected by worldwide copyright and trade secret laws and treaty
|
||||
provisions. No part of the Material may be used, copied, reproduced, modified,
|
||||
published, uploaded, posted, transmitted, distributed, or disclosed in any way
|
||||
without Intel's prior express written permission.
|
||||
|
||||
No license under any patent, copyright, trade secret or other intellectual
|
||||
property right is granted to or conferred upon you by disclosure or delivery
|
||||
of the Materials, either expressly, by implication, inducement, estoppel or
|
||||
otherwise. Any license under such intellectual property rights must be
|
||||
express and approved by Intel in writing.
|
||||
|
||||
Unless otherwise agreed by Intel in writing, you may not remove or alter
|
||||
this notice or any other notice embedded in Materials by Intel or
|
||||
Intel's suppliers or licensors in any way.
|
||||
|
||||
This file contains an 'Intel Peripheral Driver' and is uniquely identified as
|
||||
"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
|
||||
the terms of your license agreement with Intel or your vendor. This file may
|
||||
be modified by the user, subject to additional terms of the license agreement.
|
||||
|
||||
@par Specification Reference:
|
||||
**/
|
||||
#ifndef _MEM_INFO_HOB_H_
|
||||
#define _MEM_INFO_HOB_H_
|
||||
|
||||
|
||||
#pragma pack (push, 1)
|
||||
|
||||
extern EFI_GUID gSiMemoryS3DataGuid;
|
||||
extern EFI_GUID gSiMemoryS3Data2Guid;
|
||||
extern EFI_GUID gSiMemoryInfoDataGuid;
|
||||
extern EFI_GUID gSiMemoryPlatformDataGuid;
|
||||
|
||||
#define MAX_NODE 2
|
||||
#define MAX_CH 4
|
||||
#define MAX_DDR5_CH 2
|
||||
#define MAX_DIMM 2
|
||||
// Must match definitions in
|
||||
// Intel\ClientOneSiliconPkg\IpBlock\MemoryInit\Mtl\Include\MrcInterface.h
|
||||
#define HOB_MAX_SAGV_POINTS 4
|
||||
|
||||
///
|
||||
/// Host reset states from MRC.
|
||||
///
|
||||
#define WARM_BOOT 2
|
||||
|
||||
#define R_MC_CHNL_RANK_PRESENT 0x7C
|
||||
#define B_RANK0_PRS BIT0
|
||||
#define B_RANK1_PRS BIT1
|
||||
#define B_RANK2_PRS BIT4
|
||||
#define B_RANK3_PRS BIT5
|
||||
|
||||
// @todo remove and use the MdePkg\Include\Pi\PiHob.h
|
||||
#if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__)
|
||||
#ifndef __HOB__H__
|
||||
typedef struct _EFI_HOB_GENERIC_HEADER {
|
||||
UINT16 HobType;
|
||||
UINT16 HobLength;
|
||||
UINT32 Reserved;
|
||||
} EFI_HOB_GENERIC_HEADER;
|
||||
|
||||
typedef struct _EFI_HOB_GUID_TYPE {
|
||||
EFI_HOB_GENERIC_HEADER Header;
|
||||
EFI_GUID Name;
|
||||
///
|
||||
/// Guid specific data goes here
|
||||
///
|
||||
} EFI_HOB_GUID_TYPE;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
///
|
||||
/// Defines taken from MRC so avoid having to include MrcInterface.h
|
||||
///
|
||||
|
||||
//
|
||||
// Matches MAX_SPD_SAVE define in MRC
|
||||
//
|
||||
#ifndef MAX_SPD_SAVE
|
||||
#define MAX_SPD_SAVE 29
|
||||
#endif
|
||||
|
||||
//
|
||||
// MRC version description.
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 Major; ///< Major version number
|
||||
UINT8 Minor; ///< Minor version number
|
||||
UINT8 Rev; ///< Revision number
|
||||
UINT8 Build; ///< Build number
|
||||
} SiMrcVersion;
|
||||
|
||||
//
|
||||
// Matches MrcChannelSts enum in MRC
|
||||
//
|
||||
#ifndef CHANNEL_NOT_PRESENT
|
||||
#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller.
|
||||
#endif
|
||||
#ifndef CHANNEL_DISABLED
|
||||
#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled.
|
||||
#endif
|
||||
#ifndef CHANNEL_PRESENT
|
||||
#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled.
|
||||
#endif
|
||||
|
||||
//
|
||||
// Matches MrcDimmSts enum in MRC
|
||||
//
|
||||
#ifndef DIMM_ENABLED
|
||||
#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected.
|
||||
#endif
|
||||
#ifndef DIMM_DISABLED
|
||||
#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence.
|
||||
#endif
|
||||
#ifndef DIMM_PRESENT
|
||||
#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used.
|
||||
#endif
|
||||
#ifndef DIMM_NOT_PRESENT
|
||||
#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair.
|
||||
#endif
|
||||
|
||||
//
|
||||
// Matches MrcBootMode enum in MRC
|
||||
//
|
||||
#ifndef __MRC_BOOT_MODE__
|
||||
#define __MRC_BOOT_MODE__ //The below values are originated from MrcCommonTypes.h
|
||||
#ifndef INT32_MAX
|
||||
#define INT32_MAX (0x7FFFFFFF)
|
||||
#endif //INT32_MAX
|
||||
typedef enum {
|
||||
bmCold, ///< Cold boot
|
||||
bmWarm, ///< Warm boot
|
||||
bmS3, ///< S3 resume
|
||||
bmFast, ///< Fast boot
|
||||
MrcBootModeMax, ///< MRC_BOOT_MODE enumeration maximum value.
|
||||
MrcBootModeDelim = INT32_MAX ///< This value ensures the enum size is consistent on both sides of the PPI.
|
||||
} MRC_BOOT_MODE;
|
||||
#endif //__MRC_BOOT_MODE__
|
||||
|
||||
//
|
||||
// Matches MrcDdrType enum in MRC
|
||||
//
|
||||
#ifndef MRC_DDR_TYPE_DDR5
|
||||
#define MRC_DDR_TYPE_DDR5 1
|
||||
#endif
|
||||
#ifndef MRC_DDR_TYPE_LPDDR5
|
||||
#define MRC_DDR_TYPE_LPDDR5 2
|
||||
#endif
|
||||
#ifndef MRC_DDR_TYPE_LPDDR4
|
||||
#define MRC_DDR_TYPE_LPDDR4 3
|
||||
#endif
|
||||
#ifndef MRC_DDR_TYPE_UNKNOWN
|
||||
#define MRC_DDR_TYPE_UNKNOWN 4
|
||||
#endif
|
||||
|
||||
#define MAX_PROFILE_NUM 7 // number of memory profiles supported
|
||||
#define MAX_XMP_PROFILE_NUM 5 // number of XMP profiles supported
|
||||
|
||||
#ifndef MAX_RCOMP_TARGETS
|
||||
#define MAX_RCOMP_TARGETS 5
|
||||
#endif
|
||||
|
||||
#ifndef MAX_ODT_ENTRIES
|
||||
#define MAX_ODT_ENTRIES 11
|
||||
#endif
|
||||
|
||||
#define MAX_TRACE_REGION 5
|
||||
#define MAX_TRACE_CACHE_TYPE 2
|
||||
|
||||
//
|
||||
// DIMM timings
|
||||
//
|
||||
typedef struct {
|
||||
UINT32 tCK; ///< Memory cycle time, in femtoseconds.
|
||||
UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode.
|
||||
UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency.
|
||||
UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
|
||||
UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
|
||||
UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
|
||||
UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.
|
||||
UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
|
||||
UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
|
||||
UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time.
|
||||
UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
|
||||
UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
|
||||
UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
|
||||
UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
|
||||
UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.
|
||||
UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.
|
||||
UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
|
||||
UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time.
|
||||
UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
|
||||
UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
|
||||
UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
|
||||
UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
|
||||
UINT16 tCCD_L_WR; ///< Number of tCK cycles for the channel DIMM's minimum Write-to-Write delay for same bank group.
|
||||
} MRC_CH_TIMING;
|
||||
|
||||
typedef struct {
|
||||
UINT16 tRDPRE; ///< Read CAS to Precharge cmd delay
|
||||
} MRC_IP_TIMING;
|
||||
|
||||
///
|
||||
/// Memory SMBIOS & OC Memory Data Hob
|
||||
///
|
||||
typedef struct {
|
||||
UINT8 Status; ///< See MrcDimmStatus for the definition of this field.
|
||||
UINT8 DimmId;
|
||||
UINT32 DimmCapacity; ///< DIMM size in MBytes.
|
||||
UINT16 MfgId;
|
||||
UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DDR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
|
||||
UINT8 RankInDimm; ///< The number of ranks in this DIMM.
|
||||
UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
|
||||
UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
|
||||
UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
|
||||
UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
|
||||
UINT16 Speed; ///< The maximum capable speed of the device, in MHz
|
||||
UINT8 MdSocket; ///< MdSocket: 0 = Memory Down, 1 = Socketed. Needed for SMBIOS structure creation.
|
||||
} DIMM_INFO;
|
||||
|
||||
typedef struct {
|
||||
UINT8 Status; ///< Indicates whether this channel should be used.
|
||||
UINT8 ChannelId;
|
||||
UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.
|
||||
MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
|
||||
DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics.
|
||||
} CHANNEL_INFO;
|
||||
|
||||
typedef struct {
|
||||
UINT8 Status; ///< Indicates whether this controller should be used.
|
||||
UINT16 DeviceId; ///< The PCI device id of this memory controller.
|
||||
UINT8 RevisionId; ///< The PCI revision id of this memory controller.
|
||||
UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
|
||||
CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions.
|
||||
} CONTROLLER_INFO;
|
||||
|
||||
typedef struct {
|
||||
UINT64 BaseAddress; ///< Trace Base Address
|
||||
UINT64 TotalSize; ///< Total Trace Region of Same Cache type
|
||||
UINT8 CacheType; ///< Trace Cache Type
|
||||
UINT8 ErrorCode; ///< Trace Region Allocation Fail Error code
|
||||
UINT8 Rsvd[2];
|
||||
} PSMI_MEM_INFO;
|
||||
|
||||
/// This data structure contains per-SaGv timing values that are considered output by the MRC.
|
||||
typedef struct {
|
||||
UINT32 DataRate; ///< The memory rate for the current SaGv Point in units of MT/s
|
||||
MRC_CH_TIMING JedecTiming; ///< Timings used for this entry's corresponding SaGv Point - derived from JEDEC SPD spec
|
||||
MRC_IP_TIMING IpTiming; ///< Timings used for this entry's corresponding SaGv Point - IP specific
|
||||
} HOB_SAGV_TIMING_OUT;
|
||||
|
||||
/// This data structure contains SAGV config values that are considered output by the MRC.
|
||||
typedef struct {
|
||||
UINT32 NumSaGvPointsEnabled; ///< Count of the total number of SAGV Points enabled.
|
||||
UINT32 SaGvPointMask; ///< Bit mask where each bit indicates an enabled SAGV point.
|
||||
HOB_SAGV_TIMING_OUT SaGvTiming[HOB_MAX_SAGV_POINTS];
|
||||
} HOB_SAGV_INFO;
|
||||
|
||||
typedef struct {
|
||||
UINT8 Revision;
|
||||
UINT16 DataWidth; ///< Data width, in bits, of this memory device
|
||||
/** As defined in SMBIOS 3.0 spec
|
||||
Section 7.18.2 and Table 75
|
||||
**/
|
||||
UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3
|
||||
UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz)
|
||||
UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz)
|
||||
/** As defined in SMBIOS 3.0 spec
|
||||
Section 7.17.3 and Table 72
|
||||
**/
|
||||
UINT8 ErrorCorrectionType;
|
||||
|
||||
SiMrcVersion Version;
|
||||
BOOLEAN EccSupport;
|
||||
UINT8 MemoryProfile;
|
||||
UINT32 TotalPhysicalMemorySize;
|
||||
UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist.
|
||||
UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.
|
||||
UINT8 XmpConfigWarning; ///< If XMP capable DIMMs config support only 1DPC, but 2DPC is installed
|
||||
BOOLEAN DynamicMemoryBoostTrainingFailed; ///< TRUE if Dynamic Memory Boost failed to train and was force disabled on the last full training boot. FALSE otherwise.
|
||||
UINT16 Ratio; ///< DDR Frequency Ratio, used for programs that require ratios higher then 255
|
||||
UINT8 RefClk;
|
||||
UINT32 VddVoltage[MAX_PROFILE_NUM];
|
||||
UINT32 VddqVoltage[MAX_PROFILE_NUM];
|
||||
UINT32 VppVoltage[MAX_PROFILE_NUM];
|
||||
UINT16 RcompTarget[MAX_PROFILE_NUM][MAX_RCOMP_TARGETS];
|
||||
UINT16 DimmOdt[MAX_PROFILE_NUM][MAX_DIMM][MAX_ODT_ENTRIES];
|
||||
CONTROLLER_INFO Controller[MAX_NODE];
|
||||
UINT32 NumPopulatedChannels; ///< Total number of memory channels populated
|
||||
HOB_SAGV_INFO SagvConfigInfo; ///< This data structure contains SAGV config values that are considered output by the MRC.
|
||||
BOOLEAN IsIbeccEnabled;
|
||||
UINT16 TotalMemWidth; ///< Total Memory Width in bits from all populated channels
|
||||
UINT16 PprDetectedErrors; ///< PPR: Counts of detected bad rows
|
||||
UINT16 PprRepairFails; ///< PPR: Counts of repair failure
|
||||
UINT16 PprForceRepairStatus; ///< PPR: Force Repair Status
|
||||
} MEMORY_INFO_DATA_HOB;
|
||||
|
||||
/**
|
||||
Memory Platform Data Hob
|
||||
|
||||
<b>Revision 1:</b>
|
||||
- Initial version.
|
||||
<b>Revision 2:</b>
|
||||
- Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields
|
||||
**/
|
||||
typedef struct {
|
||||
UINT8 Revision;
|
||||
UINT8 Reserved[3];
|
||||
UINT32 BootMode;
|
||||
UINT32 TsegSize;
|
||||
UINT32 TsegBase;
|
||||
UINT32 PrmrrSize;
|
||||
UINT64 PrmrrBase;
|
||||
UINT32 GttBase;
|
||||
UINT32 MmioSize;
|
||||
UINT32 PciEBaseAddress;
|
||||
PSMI_MEM_INFO PsmiInfo[MAX_TRACE_CACHE_TYPE];
|
||||
PSMI_MEM_INFO PsmiRegionInfo[MAX_TRACE_REGION];
|
||||
BOOLEAN MrcBasicMemoryTestPass;
|
||||
} MEMORY_PLATFORM_DATA;
|
||||
|
||||
typedef struct {
|
||||
EFI_HOB_GUID_TYPE EfiHobGuidType;
|
||||
MEMORY_PLATFORM_DATA Data;
|
||||
UINT8 *Buffer;
|
||||
} MEMORY_PLATFORM_DATA_HOB;
|
||||
|
||||
#pragma pack (pop)
|
||||
|
||||
#endif // _MEM_INFO_HOB_H_
|
||||
@ -0,0 +1,56 @@
|
||||
/** @file
|
||||
Header file for SMBIOS Cache Info HOB
|
||||
|
||||
@copyright
|
||||
INTEL CONFIDENTIAL
|
||||
Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License which accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
System Management BIOS (SMBIOS) Reference Specification v3.1.0
|
||||
dated 2016-Nov-16 (DSP0134)
|
||||
http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.1.0.pdf
|
||||
**/
|
||||
|
||||
#ifndef _SMBIOS_CACHE_INFO_HOB_H_
|
||||
#define _SMBIOS_CACHE_INFO_HOB_H_
|
||||
|
||||
#include <Uefi.h>
|
||||
#include <Pi/PiHob.h>
|
||||
|
||||
#pragma pack(1)
|
||||
///
|
||||
/// SMBIOS Cache Info HOB Structure
|
||||
///
|
||||
typedef struct {
|
||||
UINT16 ProcessorSocketNumber;
|
||||
UINT16 NumberOfCacheLevels; ///< Based on Number of Cache Types L1/L2/L3
|
||||
UINT8 SocketDesignationStrIndex; ///< String Index in the string Buffer. Example "L1-CACHE"
|
||||
UINT16 CacheConfiguration; ///< Format defined in SMBIOS Spec v3.1 Section7.8 Table36
|
||||
UINT16 MaxCacheSize; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1
|
||||
UINT16 InstalledSize; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1
|
||||
UINT16 SupportedSramType; ///< Format defined in SMBIOS Spec v3.1 Section7.8.2
|
||||
UINT16 CurrentSramType; ///< Format defined in SMBIOS Spec v3.1 Section7.8.2
|
||||
UINT8 CacheSpeed; ///< Cache Speed in nanoseconds. 0 if speed is unknown.
|
||||
UINT8 ErrorCorrectionType; ///< ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.3
|
||||
UINT8 SystemCacheType; ///< ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.4
|
||||
UINT8 Associativity; ///< ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.5
|
||||
//
|
||||
// Add for smbios 3.1.0
|
||||
//
|
||||
UINT32 MaximumCacheSize2; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1
|
||||
UINT32 InstalledSize2; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1
|
||||
/**
|
||||
String Buffer - each string terminated by NULL "0x00"
|
||||
String buffer terminated by double NULL "0x0000"
|
||||
**/
|
||||
} SMBIOS_CACHE_INFO;
|
||||
#pragma pack()
|
||||
|
||||
#endif // _SMBIOS_CACHE_INFO_HOB_H_
|
||||
@ -0,0 +1,67 @@
|
||||
/** @file
|
||||
Header file for SMBIOS Processor Info HOB
|
||||
|
||||
@copyright
|
||||
INTEL CONFIDENTIAL
|
||||
Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
System Management BIOS (SMBIOS) Reference Specification v3.1.0
|
||||
dated 2016-Nov-16 (DSP0134)
|
||||
http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.1.0.pdf
|
||||
**/
|
||||
|
||||
#ifndef _SMBIOS_PROCESSOR_INFO_HOB_H_
|
||||
#define _SMBIOS_PROCESSOR_INFO_HOB_H_
|
||||
|
||||
#include <Uefi.h>
|
||||
#include <Pi/PiHob.h>
|
||||
|
||||
#pragma pack(1)
|
||||
///
|
||||
/// SMBIOS Processor Info HOB Structure
|
||||
///
|
||||
typedef struct {
|
||||
UINT16 TotalNumberOfSockets;
|
||||
UINT16 CurrentSocketNumber;
|
||||
UINT8 ProcessorType; ///< ENUM defined in SMBIOS Spec v3.1 Section 7.5.1
|
||||
/** This info is used for both ProcessorFamily and ProcessorFamily2 fields
|
||||
See ENUM defined in SMBIOS Spec v3.1 Section 7.5.2
|
||||
**/
|
||||
UINT16 ProcessorFamily;
|
||||
UINT8 ProcessorManufacturerStrIndex; ///< Index of the String in the String Buffer
|
||||
UINT64 ProcessorId; ///< ENUM defined in SMBIOS Spec v3.1 Section 7.5.3
|
||||
UINT8 ProcessorVersionStrIndex; ///< Index of the String in the String Buffer
|
||||
UINT8 Voltage; ///< Format defined in SMBIOS Spec v3.1 Section 7.5.4
|
||||
UINT16 ExternalClockInMHz; ///< External Clock Frequency. Set to 0 if unknown.
|
||||
UINT16 MaxSpeedInMHz; ///< Snapshot of Max processor speed during boot
|
||||
UINT16 CurrentSpeedInMHz; ///< Snapshot of current processor speed during boot
|
||||
UINT8 Status; ///< Format defined in the SMBIOS Spec v3.1 Table 21
|
||||
UINT8 ProcessorUpgrade; ///< ENUM defined in SMBIOS Spec v3.1 Section 7.5.5
|
||||
/** This info is used for both CoreCount & CoreCount2 fields
|
||||
See detailed description in SMBIOS Spec v3.1 Section 7.5.6
|
||||
**/
|
||||
UINT16 CoreCount;
|
||||
/** This info is used for both CoreEnabled & CoreEnabled2 fields
|
||||
See detailed description in SMBIOS Spec v3.1 Section 7.5.7
|
||||
**/
|
||||
UINT16 EnabledCoreCount;
|
||||
/** This info is used for both ThreadCount & ThreadCount2 fields
|
||||
See detailed description in SMBIOS Spec v3.1 Section 7.5.8
|
||||
**/
|
||||
UINT16 ThreadCount;
|
||||
UINT16 ProcessorCharacteristics; ///< Format defined in SMBIOS Spec v3.1 Section 7.5.9
|
||||
/**
|
||||
String Buffer - each string terminated by NULL "0x00"
|
||||
String buffer terminated by double NULL "0x0000"
|
||||
**/
|
||||
} SMBIOS_PROCESSOR_INFO;
|
||||
#pragma pack()
|
||||
|
||||
#endif // _SMBIOS_PROCESSOR_INFO_HOB_H_
|
||||
@ -0,0 +1,49 @@
|
||||
/** @file
|
||||
Library instance to list all DynamicEx PCD FSP consumes.
|
||||
No real functionality.
|
||||
|
||||
@copyright
|
||||
INTEL CONFIDENTIAL
|
||||
Copyright 2019 Intel Corporation.
|
||||
|
||||
The source code contained or described herein and all documents related to the
|
||||
source code ("Material") are owned by Intel Corporation or its suppliers or
|
||||
licensors. Title to the Material remains with Intel Corporation or its suppliers
|
||||
and licensors. The Material may contain trade secrets and proprietary and
|
||||
confidential information of Intel Corporation and its suppliers and licensors,
|
||||
and is protected by worldwide copyright and trade secret laws and treaty
|
||||
provisions. No part of the Material may be used, copied, reproduced, modified,
|
||||
published, uploaded, posted, transmitted, distributed, or disclosed in any way
|
||||
without Intel's prior express written permission.
|
||||
|
||||
No license under any patent, copyright, trade secret or other intellectual
|
||||
property right is granted to or conferred upon you by disclosure or delivery
|
||||
of the Materials, either expressly, by implication, inducement, estoppel or
|
||||
otherwise. Any license under such intellectual property rights must be
|
||||
express and approved by Intel in writing.
|
||||
|
||||
Unless otherwise agreed by Intel in writing, you may not remove or alter
|
||||
this notice or any other notice embedded in Materials by Intel or
|
||||
Intel's suppliers or licensors in any way.
|
||||
|
||||
This file contains an 'Intel Peripheral Driver' and is uniquely identified as
|
||||
"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
|
||||
the terms of your license agreement with Intel or your vendor. This file may
|
||||
be modified by the user, subject to additional terms of the license agreement.
|
||||
|
||||
@par Specification Reference:
|
||||
**/
|
||||
|
||||
#include <Base.h>
|
||||
|
||||
/**
|
||||
Do nothing function.
|
||||
|
||||
**/
|
||||
VOID
|
||||
FspPcdListLibNull (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
return;
|
||||
}
|
||||
@ -0,0 +1,86 @@
|
||||
## @file
|
||||
# Library instance to list all DynamicEx PCD FSP consumes.
|
||||
#
|
||||
# @copyright
|
||||
# INTEL CONFIDENTIAL
|
||||
# Copyright 2019 - 2021 Intel Corporation.
|
||||
#
|
||||
# The source code contained or described herein and all documents related to the
|
||||
# source code ("Material") are owned by Intel Corporation or its suppliers or
|
||||
# licensors. Title to the Material remains with Intel Corporation or its suppliers
|
||||
# and licensors. The Material may contain trade secrets and proprietary and
|
||||
# confidential information of Intel Corporation and its suppliers and licensors,
|
||||
# and is protected by worldwide copyright and trade secret laws and treaty
|
||||
# provisions. No part of the Material may be used, copied, reproduced, modified,
|
||||
# published, uploaded, posted, transmitted, distributed, or disclosed in any way
|
||||
# without Intel's prior express written permission.
|
||||
#
|
||||
# No license under any patent, copyright, trade secret or other intellectual
|
||||
# property right is granted to or conferred upon you by disclosure or delivery
|
||||
# of the Materials, either expressly, by implication, inducement, estoppel or
|
||||
# otherwise. Any license under such intellectual property rights must be
|
||||
# express and approved by Intel in writing.
|
||||
#
|
||||
# Unless otherwise agreed by Intel in writing, you may not remove or alter
|
||||
# this notice or any other notice embedded in Materials by Intel or
|
||||
# Intel's suppliers or licensors in any way.
|
||||
#
|
||||
# This file contains an 'Intel Peripheral Driver' and is uniquely identified as
|
||||
# "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
|
||||
# the terms of your license agreement with Intel or your vendor. This file may
|
||||
# be modified by the user, subject to additional terms of the license agreement.
|
||||
#
|
||||
# @par Specification Reference:
|
||||
#
|
||||
##
|
||||
|
||||
[Defines]
|
||||
INF_VERSION = 0x00010017
|
||||
BASE_NAME = FspPcdListLibNull
|
||||
FILE_GUID = C5D4D79E-3D5C-4EB6-899E-6F1563CB0B32
|
||||
VERSION_STRING = 1.0
|
||||
MODULE_TYPE = BASE
|
||||
LIBRARY_CLASS = NULL
|
||||
#
|
||||
# The following information is for reference only and not required by the build tools.
|
||||
#
|
||||
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
|
||||
#
|
||||
|
||||
[LibraryClasses]
|
||||
BaseLib
|
||||
|
||||
[Packages]
|
||||
MdePkg/MdePkg.dec
|
||||
MdeModulePkg/MdeModulePkg.dec
|
||||
UefiCpuPkg/UefiCpuPkg.dec
|
||||
ClientOneSiliconPkg/SiPkg.dec
|
||||
|
||||
[Sources]
|
||||
FspPcdListLibNull.c
|
||||
|
||||
[Pcd]
|
||||
#
|
||||
# List all the DynamicEx PCDs that FSP will consume.
|
||||
# FSP Dispatch mode bootloader will include this INF to ensure all the PCDs are
|
||||
# built into PCD database.
|
||||
#
|
||||
gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ## CONSUMES
|
||||
gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress ## CONSUMES
|
||||
gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength ## CONSUMES
|
||||
gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress ## CONSUMES
|
||||
gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize ## CONSUMES
|
||||
gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode ## CONSUMES
|
||||
gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate ## CONSUMES
|
||||
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable ## CONSUMES
|
||||
gUefiCpuPkgTokenSpaceGuid.PcdCpuS3DataAddress ## CONSUMES
|
||||
gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSetting ## CONSUMES
|
||||
gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize ## CONSUMES
|
||||
gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme ## CONSUMES
|
||||
gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesCapability ## CONSUMES
|
||||
gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase ## CONSUMES
|
||||
gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr ## CONSUMES
|
||||
gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr ## CONSUMES
|
||||
gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize ## CONSUMES
|
||||
gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled ## CONSUMES
|
||||
|
||||
43
models/lemp13/MeteorLakeFspBinPkg/MeteorLakeFspBinPkg.dec
Normal file
43
models/lemp13/MeteorLakeFspBinPkg/MeteorLakeFspBinPkg.dec
Normal file
@ -0,0 +1,43 @@
|
||||
## @file
|
||||
# Component description file for MeteorLake Fsp Bin package.
|
||||
#
|
||||
# @copyright
|
||||
# INTEL CONFIDENTIAL
|
||||
# Copyright 2016 - 2019 Intel Corporation.
|
||||
#
|
||||
# The source code contained or described herein and all documents related to the
|
||||
# source code ("Material") are owned by Intel Corporation or its suppliers or
|
||||
# licensors. Title to the Material remains with Intel Corporation or its suppliers
|
||||
# and licensors. The Material may contain trade secrets and proprietary and
|
||||
# confidential information of Intel Corporation and its suppliers and licensors,
|
||||
# and is protected by worldwide copyright and trade secret laws and treaty
|
||||
# provisions. No part of the Material may be used, copied, reproduced, modified,
|
||||
# published, uploaded, posted, transmitted, distributed, or disclosed in any way
|
||||
# without Intel's prior express written permission.
|
||||
#
|
||||
# No license under any patent, copyright, trade secret or other intellectual
|
||||
# property right is granted to or conferred upon you by disclosure or delivery
|
||||
# of the Materials, either expressly, by implication, inducement, estoppel or
|
||||
# otherwise. Any license under such intellectual property rights must be
|
||||
# express and approved by Intel in writing.
|
||||
#
|
||||
# Unless otherwise agreed by Intel in writing, you may not remove or alter
|
||||
# this notice or any other notice embedded in Materials by Intel or
|
||||
# Intel's suppliers or licensors in any way.
|
||||
#
|
||||
# This file contains an 'Intel Peripheral Driver' and is uniquely identified as
|
||||
# "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
|
||||
# the terms of your license agreement with Intel or your vendor. This file may
|
||||
# be modified by the user, subject to additional terms of the license agreement.
|
||||
#
|
||||
# @par Specification
|
||||
##
|
||||
|
||||
[Defines]
|
||||
DEC_SPECIFICATION = 0x00010005
|
||||
PACKAGE_NAME = MeteorLakeFspBinPkg
|
||||
PACKAGE_GUID = 5A536013-A46E-44AD-8B30-738235F77B06
|
||||
PACKAGE_VERSION = 1.02
|
||||
|
||||
[Includes]
|
||||
Include
|
||||
12
models/lemp13/README.md
Normal file
12
models/lemp13/README.md
Normal file
@ -0,0 +1,12 @@
|
||||
# System76 Lemur Pro (lemp13)
|
||||
|
||||
## Contents
|
||||
|
||||
- [EC](./ec.rom)
|
||||
- *Read Error: No such file or directory (os error 2)*
|
||||
- [FD](./fd.rom)
|
||||
- Size: 16 KB
|
||||
- HAP: true
|
||||
- [ME](./me.rom)
|
||||
- Size: 10128 KB
|
||||
- Version: 18.0.5.2066
|
||||
1
models/lemp13/README.md.in
Normal file
1
models/lemp13/README.md.in
Normal file
@ -0,0 +1 @@
|
||||
# System76 Lemur Pro (lemp13)
|
||||
1
models/lemp13/chip.txt
Normal file
1
models/lemp13/chip.txt
Normal file
@ -0,0 +1 @@
|
||||
XM25QU256C
|
||||
260
models/lemp13/coreboot-collector.txt
Normal file
260
models/lemp13/coreboot-collector.txt
Normal file
@ -0,0 +1,260 @@
|
||||
## PCI ##
|
||||
PCI Device: 0000:00:00.0: Class 0x00060000, Vendor 0x8086, Device 0x7D02, Revision 0x04
|
||||
PCI Device: 0000:00:02.0: Class 0x00030000, Vendor 0x8086, Device 0x7D45, Revision 0x08
|
||||
PCI Device: 0000:00:04.0: Class 0x00118000, Vendor 0x8086, Device 0x7D03, Revision 0x04
|
||||
PCI Device: 0000:00:07.0: Class 0x00060400, Vendor 0x8086, Device 0x7EC4, Revision 0x10
|
||||
PCI Device: 0000:00:08.0: Class 0x00088000, Vendor 0x8086, Device 0x7E4C, Revision 0x20
|
||||
PCI Device: 0000:00:0a.0: Class 0x00118000, Vendor 0x8086, Device 0x7D0D, Revision 0x01
|
||||
PCI Device: 0000:00:0b.0: Class 0x00120000, Vendor 0x8086, Device 0x7D1D, Revision 0x04
|
||||
PCI Device: 0000:00:0d.0: Class 0x000C0330, Vendor 0x8086, Device 0x7EC0, Revision 0x10
|
||||
PCI Device: 0000:00:0d.2: Class 0x000C0340, Vendor 0x8086, Device 0x7EC2, Revision 0x10
|
||||
PCI Device: 0000:00:0e.0: Class 0x00010400, Vendor 0x8086, Device 0x7D0B, Revision 0x00
|
||||
PCI Device: 0000:00:14.0: Class 0x000C0330, Vendor 0x8086, Device 0x7E7D, Revision 0x20
|
||||
PCI Device: 0000:00:14.2: Class 0x00050000, Vendor 0x8086, Device 0x7E7F, Revision 0x20
|
||||
PCI Device: 0000:00:14.3: Class 0x00028000, Vendor 0x8086, Device 0x7E40, Revision 0x20
|
||||
PCI Device: 0000:00:15.0: Class 0x000C8000, Vendor 0x8086, Device 0x7E78, Revision 0x20
|
||||
PCI Device: 0000:00:15.1: Class 0x000C8000, Vendor 0x8086, Device 0x7E79, Revision 0x20
|
||||
PCI Device: 0000:00:16.0: Class 0x00078000, Vendor 0x8086, Device 0x7E70, Revision 0x20
|
||||
PCI Device: 0000:00:16.3: Class 0x00070002, Vendor 0x8086, Device 0x7E73, Revision 0x20
|
||||
PCI Device: 0000:00:19.0: Class 0x000C8000, Vendor 0x8086, Device 0x7E50, Revision 0x20
|
||||
PCI Device: 0000:00:19.1: Class 0x000C8000, Vendor 0x8086, Device 0x7E51, Revision 0x20
|
||||
PCI Device: 0000:00:1c.0: Class 0x00060400, Vendor 0x8086, Device 0x7E38, Revision 0x20
|
||||
PCI Device: 0000:00:1f.0: Class 0x00060100, Vendor 0x8086, Device 0x7E03, Revision 0x20
|
||||
PCI Device: 0000:00:1f.3: Class 0x00040380, Vendor 0x8086, Device 0x7E28, Revision 0x20
|
||||
PCI Device: 0000:00:1f.4: Class 0x000C0500, Vendor 0x8086, Device 0x7E22, Revision 0x20
|
||||
PCI Device: 0000:00:1f.5: Class 0x000C8000, Vendor 0x8086, Device 0x7E23, Revision 0x20
|
||||
PCI Device: 0000:2b:00.0: Class 0x00080501, Vendor 0x1217, Device 0x8621, Revision 0x01
|
||||
PCI Device: 10000:e0:06.0: Class 0x00088000, Vendor 0x8086, Device 0x09AB, Revision 0x00
|
||||
PCI Device: 10000:e0:06.1: Class 0x00060400, Vendor 0x8086, Device 0x7ECA, Revision 0x10
|
||||
PCI Device: 10000:e1:00.0: Class 0x00010802, Vendor 0x144D, Device 0xA80A, Revision 0x00
|
||||
## GPIO ##
|
||||
MTL-H/U PCH
|
||||
GPP_V0 (0xD1,0x00) 0x40000700 0x0003c000 0x00000000 0x00000000
|
||||
GPP_V1 (0xD1,0x02) 0x40000700 0x0003c000 0x00000000 0x00000000
|
||||
GPP_V2 (0xD1,0x04) 0x40000702 0x0003c000 0x00000000 0x00000000
|
||||
GPP_V3 (0xD1,0x06) 0x40000700 0x0003c000 0x00000000 0x00000000
|
||||
GPP_V4 (0xD1,0x08) 0x40000702 0x0003c000 0x00000000 0x00000000
|
||||
GPP_V5 (0xD1,0x0A) 0x44000702 0x0003f018 0x00000000 0x00000000
|
||||
GPP_V6 (0xD1,0x0C) 0x44000702 0x0003fc19 0x00000000 0x00000000
|
||||
GPP_V7 (0xD1,0x0E) 0x44000102 0x0003fc1a 0x00000000 0x00000000
|
||||
GPP_V8 (0xD1,0x10) 0x44000702 0x0003c01b 0x00000000 0x00000000
|
||||
GPP_V9 (0xD1,0x12) 0x44000600 0x0003c01c 0x00000000 0x00000000
|
||||
GPP_V10 (0xD1,0x14) 0x44000600 0x0003c01d 0x00000000 0x00000000
|
||||
GPP_V11 (0xD1,0x16) 0x44000600 0x0003c01e 0x00000000 0x00000000
|
||||
GPP_V12 (0xD1,0x18) 0x44000300 0x0000001f 0x00000000 0x00000000
|
||||
GPP_V13 (0xD1,0x1A) 0x44000600 0x0003c020 0x00000000 0x00000000
|
||||
GPP_V14 (0xD1,0x1C) 0x44000600 0x0003c021 0x00000000 0x00000000
|
||||
GPP_V15 (0xD1,0x1E) 0x84000600 0x0003c022 0x00000000 0x00000000
|
||||
GPP_V16 (0xD1,0x20) 0x84000200 0x0003c023 0x00000000 0x00000000
|
||||
GPP_V17 (0xD1,0x22) 0x84000200 0x0003c024 0x00000000 0x00000000
|
||||
GPP_V18 (0xD1,0x24) 0x44000300 0x00000025 0x00000000 0x00000000
|
||||
GPP_V19 (0xD1,0x26) 0x44000702 0x0003c026 0x00000000 0x00000000
|
||||
GPP_V20 (0xD1,0x28) 0x44000300 0x00000027 0x00000000 0x00000000
|
||||
GPP_V21 (0xD1,0x2A) 0x44000300 0x00000028 0x00000000 0x00000000
|
||||
GPP_V22 (0xD1,0x2C) 0x44000300 0x00000029 0x00000000 0x00000000
|
||||
GPP_V23 (0xD1,0x2E) 0x44000300 0x0000002a 0x00000000 0x00000000
|
||||
GPP_C0 (0xD1,0x30) 0x44000600 0x0003c02b 0x00000000 0x00000000
|
||||
GPP_C1 (0xD1,0x32) 0x44000602 0x0003c02c 0x00000000 0x00000000
|
||||
GPP_C2 (0xD1,0x34) 0x44000600 0x0003c02d 0x00000000 0x00000000
|
||||
GPP_C3 (0xD1,0x36) 0x84000200 0x0003c02e 0x00000000 0x00000000
|
||||
GPP_C4 (0xD1,0x38) 0x84000200 0x0003c02f 0x00000000 0x00000000
|
||||
GPP_C5 (0xD1,0x3A) 0x44000702 0x0003f030 0x00000000 0x00000000
|
||||
GPP_C6 (0xD1,0x3C) 0x44000702 0x0003f031 0x00000000 0x00000000
|
||||
GPP_C7 (0xD1,0x3E) 0x44000102 0x00000032 0x00000800 0x00000000
|
||||
GPP_C8 (0xD1,0x40) 0x44000702 0x0003c033 0x00000000 0x00000000
|
||||
GPP_C9 (0xD1,0x42) 0x44000702 0x0003c034 0x00000000 0x00000000
|
||||
GPP_C10 (0xD1,0x44) 0x84000200 0x00000035 0x00000000 0x00000000
|
||||
GPP_C11 (0xD1,0x46) 0x04000702 0x0003c036 0x00000000 0x00000000
|
||||
GPP_C12 (0xD1,0x48) 0x04000702 0x0003c037 0x00000000 0x00000000
|
||||
GPP_C13 (0xD1,0x4A) 0x44000003 0x00000038 0x00000000 0x00000000
|
||||
GPP_C14 (0xD1,0x4C) 0x44000702 0x00000039 0x00000000 0x00000000
|
||||
GPP_C15 (0xD1,0x4E) 0x44000702 0x0000003a 0x00000000 0x00000000
|
||||
GPP_C16 (0xD1,0x50) 0x44000702 0x0000003b 0x00000000 0x00000000
|
||||
GPP_C17 (0xD1,0x52) 0x44000300 0x0000003c 0x00000000 0x00000000
|
||||
GPP_C18 (0xD1,0x54) 0x44000300 0x0000003d 0x00000000 0x00000000
|
||||
GPP_C19 (0xD1,0x56) 0x44000300 0x0000003e 0x00000000 0x00000000
|
||||
GPP_C20 (0xD1,0x58) 0x84000200 0x0000003f 0x00000000 0x00000000
|
||||
GPP_C21 (0xD1,0x5A) 0x44000700 0x00024040 0x00000000 0x00000000
|
||||
GPP_C22 (0xD1,0x5C) 0x44000700 0x00024041 0x00000000 0x00000000
|
||||
GPP_C23 (0xD1,0x5E) 0x84000200 0x00000042 0x00000000 0x00000000
|
||||
GPP_A0 (0xD2,0x00) 0x44000700 0x0003f048 0x00000000 0x00000000
|
||||
GPP_A1 (0xD2,0x02) 0x44000702 0x0003f049 0x00000000 0x00000000
|
||||
GPP_A2 (0xD2,0x04) 0x44000700 0x0003f04a 0x00000000 0x00000000
|
||||
GPP_A3 (0xD2,0x06) 0x44000700 0x0003f04b 0x00000000 0x00000000
|
||||
GPP_A4 (0xD2,0x08) 0x44000700 0x0003f04c 0x00000000 0x00000000
|
||||
GPP_A5 (0xD2,0x0A) 0x44000700 0x0003f04d 0x00000000 0x00000000
|
||||
GPP_A6 (0xD2,0x0C) 0x44000700 0x0003c04e 0x00000000 0x00000000
|
||||
GPP_A7 (0xD2,0x0E) 0x44000300 0x0000004f 0x00000000 0x00000000
|
||||
GPP_A8 (0xD2,0x10) 0x44000300 0x00000050 0x00000000 0x00000000
|
||||
GPP_A9 (0xD2,0x12) 0x44000300 0x00000051 0x00000000 0x00000000
|
||||
GPP_A10 (0xD2,0x14) 0x44000300 0x00000052 0x00000000 0x00000000
|
||||
GPP_A11 (0xD2,0x16) 0x84000200 0x00000053 0x00000000 0x00000000
|
||||
GPP_A12 (0xD2,0x18) 0x44000300 0x00000054 0x00000000 0x00000000
|
||||
GPP_A13 (0xD2,0x1A) 0x84000201 0x00003055 0x00000000 0x00000000
|
||||
GPP_A14 (0xD2,0x1C) 0x84000200 0x00003056 0x00000000 0x00000000
|
||||
GPP_A15 (0xD2,0x1E) 0x84000200 0x00003057 0x00000000 0x00000000
|
||||
GPP_A16 (0xD2,0x20) 0x44000702 0x0003f058 0x00000000 0x00000000
|
||||
GPP_A17 (0xD2,0x22) 0x40100102 0x00000059 0x00000000 0x00000000
|
||||
GPP_A18 (0xD2,0x24) 0x84000200 0x0000305a 0x00000000 0x00000000
|
||||
GPP_A19 (0xD2,0x26) 0x44000200 0x0000305b 0x00000000 0x00000000
|
||||
GPP_A20 (0xD2,0x28) 0x44000200 0x00003c5c 0x00000000 0x00000000
|
||||
GPP_A21 (0xD2,0x2A) 0x44000702 0x0003fc5d 0x00000000 0x00000000
|
||||
GPP_E0 (0xD2,0x32) 0x84000200 0x00000060 0x00000000 0x00000000
|
||||
GPP_E1 (0xD2,0x34) 0x40100102 0x00001061 0x00000000 0x00000000
|
||||
GPP_E2 (0xD2,0x36) 0x44000100 0x00000062 0x00000000 0x00000000
|
||||
GPP_E3 (0xD2,0x38) 0x44000300 0x00000063 0x00000000 0x00000000
|
||||
GPP_E4 (0xD2,0x3A) 0x84000200 0x00000064 0x00000000 0x00000000
|
||||
GPP_E5 (0xD2,0x3C) 0x84000200 0x00000065 0x00000000 0x00000000
|
||||
GPP_E6 (0xD2,0x3E) 0x44000102 0x00000066 0x00000800 0x00000000
|
||||
GPP_E7 (0xD2,0x40) 0x84000200 0x00000067 0x00000000 0x00000000
|
||||
GPP_E8 (0xD2,0x42) 0x84000200 0x00000068 0x00000000 0x00000000
|
||||
GPP_E9 (0xD2,0x44) 0x44000102 0x00000069 0x00000800 0x00000000
|
||||
GPP_E10 (0xD2,0x46) 0x84000200 0x0000006a 0x00000000 0x00000000
|
||||
GPP_E11 (0xD2,0x48) 0x44000100 0x0000006b 0x00000000 0x00000000
|
||||
GPP_E12 (0xD2,0x4A) 0x84002200 0x0000006c 0x00000000 0x00000000
|
||||
GPP_E13 (0xD2,0x4C) 0x44002100 0x0000006d 0x00000000 0x00000000
|
||||
GPP_E14 (0xD2,0x4E) 0x44000700 0x0002406e 0x00000000 0x00000000
|
||||
GPP_E15 (0xD2,0x50) 0x84000200 0x0000006f 0x00000000 0x00000000
|
||||
GPP_E16 (0xD2,0x52) 0x44000b02 0x0003c070 0x00000000 0x00000000
|
||||
GPP_E17 (0xD2,0x54) 0x84000200 0x00000071 0x00000000 0x00000000
|
||||
GPP_E18 (0xD2,0x56) 0x44000300 0x00000072 0x00000000 0x00000000
|
||||
GPP_E19 (0xD2,0x58) 0x44000300 0x00000073 0x00000000 0x00000000
|
||||
GPP_E20 (0xD2,0x5A) 0x44000300 0x00000074 0x00000000 0x00000000
|
||||
GPP_E21 (0xD2,0x5C) 0x44000300 0x00000075 0x00000000 0x00000000
|
||||
GPP_E22 (0xD2,0x5E) 0x84000200 0x00001076 0x00000000 0x00000000
|
||||
GPP_H0 (0xD3,0x00) 0x84000200 0x00000018 0x00000000 0x00000000
|
||||
GPP_H1 (0xD3,0x02) 0x84000200 0x00000019 0x00000000 0x00000000
|
||||
GPP_H2 (0xD3,0x04) 0x84000201 0x0000001a 0x00000000 0x00000000
|
||||
GPP_H3 (0xD3,0x06) 0x44000300 0x0000001b 0x00000000 0x00000000
|
||||
GPP_H4 (0xD3,0x08) 0x44000300 0x0000001c 0x00000000 0x00000000
|
||||
GPP_H5 (0xD3,0x0A) 0x44000300 0x0000001d 0x00000000 0x00000000
|
||||
GPP_H6 (0xD3,0x0C) 0x44000300 0x0000001e 0x00000000 0x00000000
|
||||
GPP_H7 (0xD3,0x0E) 0x44000300 0x0000001f 0x00000000 0x00000000
|
||||
GPP_H8 (0xD3,0x10) 0x44000300 0x00000020 0x00000000 0x00000000
|
||||
GPP_H9 (0xD3,0x12) 0x44000300 0x00000021 0x00000000 0x00000000
|
||||
GPP_H10 (0xD3,0x14) 0x84000200 0x00000022 0x00000000 0x00000000
|
||||
GPP_H11 (0xD3,0x16) 0x84000200 0x00000023 0x00000000 0x00000000
|
||||
GPP_H12 (0xD3,0x18) 0x44000300 0x00000024 0x00000000 0x00000000
|
||||
GPP_H13 (0xD3,0x1A) 0x44000700 0x0003c025 0x00000000 0x00000000
|
||||
GPP_H14 (0xD3,0x1C) 0x84000200 0x00000026 0x00000000 0x00000000
|
||||
GPP_H15 (0xD3,0x1E) 0x84000200 0x00000027 0x00000000 0x00000000
|
||||
GPP_H16 (0xD3,0x20) 0x84000200 0x00000028 0x00000000 0x00000000
|
||||
GPP_H17 (0xD3,0x22) 0x84000200 0x00000029 0x00000000 0x00000000
|
||||
GPP_H18 (0xD3,0x24) 0x44000300 0x0000002a 0x00000000 0x00000000
|
||||
GPP_H19 (0xD3,0x26) 0x44000702 0x0000002b 0x00000000 0x00000000
|
||||
GPP_H20 (0xD3,0x28) 0x44000702 0x0000002c 0x00000000 0x00000000
|
||||
GPP_H21 (0xD3,0x2A) 0x44000702 0x0000002d 0x00000000 0x00000000
|
||||
GPP_H22 (0xD3,0x2C) 0x44000602 0x0000002e 0x00000000 0x00000000
|
||||
GPP_F0 (0xD3,0x34) 0x44000700 0x0003c030 0x00000000 0x00000000
|
||||
GPP_F1 (0xD3,0x36) 0x44000702 0x0003f031 0x00000000 0x00000000
|
||||
GPP_F2 (0xD3,0x38) 0x44000700 0x0003c032 0x00000000 0x00000000
|
||||
GPP_F3 (0xD3,0x3A) 0x44000702 0x0003f033 0x00000000 0x00000000
|
||||
GPP_F4 (0xD3,0x3C) 0x44000700 0x0003c034 0x00000000 0x00000000
|
||||
GPP_F5 (0xD3,0x3E) 0x44000f00 0x0003c035 0x00000000 0x00000000
|
||||
GPP_F6 (0xD3,0x40) 0x44000500 0x0003c036 0x00000000 0x00000000
|
||||
GPP_F7 (0xD3,0x42) 0x44000700 0x0003d037 0x00000000 0x00000000
|
||||
GPP_F8 (0xD3,0x44) 0x44000700 0x0003d038 0x00000000 0x00000000
|
||||
GPP_F9 (0xD3,0x46) 0x44000102 0x00000039 0x00000000 0x00000000
|
||||
GPP_F10 (0xD3,0x48) 0x44000300 0x0000003a 0x00000000 0x00000000
|
||||
GPP_F11 (0xD3,0x4A) 0x84000200 0x0000003b 0x00000000 0x00000000
|
||||
GPP_F12 (0xD3,0x4C) 0x44002302 0x0000003c 0x00000000 0x00000000
|
||||
GPP_F13 (0xD3,0x4E) 0x44002302 0x0000003d 0x00000000 0x00000000
|
||||
GPP_F14 (0xD3,0x50) 0x84000200 0x0000003e 0x00000000 0x00000000
|
||||
GPP_F15 (0xD3,0x52) 0x84000200 0x0000003f 0x00000000 0x00000000
|
||||
GPP_F16 (0xD3,0x54) 0x84000200 0x00000040 0x00000000 0x00000000
|
||||
GPP_F17 (0xD3,0x56) 0x84000200 0x00000041 0x00000000 0x00000000
|
||||
GPP_F18 (0xD3,0x58) 0x44000200 0x00000042 0x00000000 0x00000000
|
||||
GPP_F19 (0xD3,0x5A) 0x84000200 0x00000043 0x00000000 0x00000000
|
||||
GPP_F20 (0xD3,0x5C) 0x84000200 0x00000044 0x00000000 0x00000000
|
||||
GPP_F21 (0xD3,0x5E) 0x84000200 0x00000045 0x00000800 0x00000000
|
||||
GPP_F22 (0xD3,0x60) 0x84000200 0x00000046 0x00000000 0x00000000
|
||||
GPP_F23 (0xD3,0x62) 0x84000200 0x00000047 0x00000000 0x00000000
|
||||
GPP_S0 (0xD4,0x00) 0x84000200 0x01800050 0x00000000 0x00000000
|
||||
GPP_S1 (0xD4,0x02) 0x84000200 0x01800051 0x00000000 0x00000000
|
||||
GPP_S2 (0xD4,0x04) 0x84000200 0x01800052 0x00000000 0x00000000
|
||||
GPP_S3 (0xD4,0x06) 0x84000200 0x01800053 0x00000000 0x00000000
|
||||
GPP_S4 (0xD4,0x08) 0x84000200 0x01800054 0x00000000 0x00000000
|
||||
GPP_S5 (0xD4,0x0A) 0x84000200 0x01800055 0x00000000 0x00000000
|
||||
GPP_S6 (0xD4,0x0C) 0x44000f00 0x01800056 0x00000000 0x00000000
|
||||
GPP_S7 (0xD4,0x0E) 0x44000f00 0x01800057 0x00000000 0x00000000
|
||||
GPP_B0 (0xD5,0x00) 0x40100100 0x00000058 0x00000000 0x00000000
|
||||
GPP_B1 (0xD5,0x02) 0x84000200 0x00000059 0x00000000 0x00000000
|
||||
GPP_B2 (0xD5,0x04) 0x84000200 0x0000005a 0x00000000 0x00000000
|
||||
GPP_B3 (0xD5,0x06) 0x84000200 0x0000005b 0x00000000 0x00000000
|
||||
GPP_B4 (0xD5,0x08) 0x84000200 0x0000005c 0x00000000 0x00000000
|
||||
GPP_B5 (0xD5,0x0A) 0x84000201 0x0000005d 0x00000000 0x00000000
|
||||
GPP_B6 (0xD5,0x0C) 0x44000200 0x0000005e 0x00000000 0x00000000
|
||||
GPP_B7 (0xD5,0x0E) 0x44000003 0x0000005f 0x00000000 0x00000000
|
||||
GPP_B8 (0xD5,0x10) 0x44000003 0x00000060 0x00000000 0x00000000
|
||||
GPP_B9 (0xD5,0x12) 0x44000102 0x00000061 0x00000000 0x00000000
|
||||
GPP_B10 (0xD5,0x14) 0x44000102 0x00000062 0x00000000 0x00000000
|
||||
GPP_B11 (0xD5,0x16) 0x44000b02 0x00024063 0x00000000 0x00000000
|
||||
GPP_B12 (0xD5,0x18) 0x44000700 0x0003c064 0x00000000 0x00000000
|
||||
GPP_B13 (0xD5,0x1A) 0x84000700 0x0003c065 0x00000000 0x00000000
|
||||
GPP_B14 (0xD5,0x1C) 0x84000200 0x00000066 0x00000000 0x00000000
|
||||
GPP_B15 (0xD5,0x1E) 0x44000102 0x00000067 0x00000000 0x00000000
|
||||
GPP_B16 (0xD5,0x20) 0x44000102 0x00000068 0x00000000 0x00000000
|
||||
GPP_B17 (0xD5,0x22) 0x84000201 0x00000069 0x00000000 0x00000000
|
||||
GPP_B18 (0xD5,0x24) 0x84000201 0x0000006a 0x00000000 0x00000000
|
||||
GPP_B19 (0xD5,0x26) 0x84000201 0x0000006b 0x00000000 0x00000000
|
||||
GPP_B20 (0xD5,0x28) 0x84000201 0x0000006c 0x00000000 0x00000000
|
||||
GPP_B21 (0xD5,0x2A) 0x84000200 0x0000006d 0x00000000 0x00000000
|
||||
GPP_B22 (0xD5,0x2C) 0x44000100 0x0000006e 0x00000000 0x00000000
|
||||
GPP_B23 (0xD5,0x2E) 0x44000003 0x0000006f 0x00000000 0x00000000
|
||||
GPP_D0 (0xD5,0x32) 0x84000201 0x00000070 0x00000000 0x00000000
|
||||
GPP_D1 (0xD5,0x34) 0x84000201 0x00000071 0x00000000 0x00000000
|
||||
GPP_D2 (0xD5,0x36) 0x84000201 0x00000072 0x00000000 0x00000000
|
||||
GPP_D3 (0xD5,0x38) 0x44000300 0x00000073 0x00000000 0x00000000
|
||||
GPP_D4 (0xD5,0x3A) 0x84000200 0x00000074 0x00000000 0x00000000
|
||||
GPP_D5 (0xD5,0x3C) 0x84000201 0x00000075 0x00000000 0x00000000
|
||||
GPP_D6 (0xD5,0x3E) 0x84000200 0x00000076 0x00000000 0x00000000
|
||||
GPP_D7 (0xD5,0x40) 0x84000200 0x00000077 0x00000000 0x00000000
|
||||
GPP_D8 (0xD5,0x42) 0x84000200 0x00000018 0x00000000 0x00000000
|
||||
GPP_D9 (0xD5,0x44) 0x84000200 0x00000019 0x00000000 0x00000000
|
||||
GPP_D10 (0xD5,0x46) 0x44000600 0x0003c01a 0x00000000 0x00000000
|
||||
GPP_D11 (0xD5,0x48) 0x44000700 0x0003fc1b 0x00000000 0x00000000
|
||||
GPP_D12 (0xD5,0x4A) 0x44000600 0x0003fc1c 0x00000000 0x00000000
|
||||
GPP_D13 (0xD5,0x4C) 0x44000700 0x0003fc1d 0x00000000 0x00000000
|
||||
GPP_D14 (0xD5,0x4E) 0x84000200 0x0000001e 0x00000000 0x00000000
|
||||
GPP_D15 (0xD5,0x50) 0x84000200 0x0000001f 0x00000000 0x00000000
|
||||
GPP_D16 (0xD5,0x52) 0x44000200 0x00000020 0x00000000 0x00000000
|
||||
GPP_D17 (0xD5,0x54) 0x44000700 0x0003c021 0x00000000 0x00000000
|
||||
GPP_D18 (0xD5,0x56) 0x44000300 0x00000022 0x00000000 0x00000000
|
||||
GPP_D19 (0xD5,0x58) 0x44000700 0x00000023 0x00000000 0x00000000
|
||||
GPP_D20 (0xD5,0x5A) 0x44000702 0x00000024 0x00000000 0x00000000
|
||||
GPP_D21 (0xD5,0x5C) 0x44000700 0x0003c025 0x00000000 0x00000000
|
||||
GPP_D22 (0xD5,0x5E) 0x44000700 0x0003fc26 0x00000000 0x00000000
|
||||
GPP_D23 (0xD5,0x60) 0x44000702 0x0003fc27 0x00000000 0x00000000
|
||||
## HDAUDIO ##
|
||||
hdaudioC0D0
|
||||
vendor_name: Realtek
|
||||
chip_name: ALC245
|
||||
vendor_id: 0x10ec0245
|
||||
subsystem_id: 0x15582624
|
||||
revision_id: 0x100001
|
||||
0x12: 0x90a60130
|
||||
0x13: 0x40000000
|
||||
0x14: 0x411111f0
|
||||
0x17: 0x90170110
|
||||
0x18: 0x411111f0
|
||||
0x19: 0x411111f0
|
||||
0x1a: 0x411111f0
|
||||
0x1b: 0x411111f0
|
||||
0x1d: 0x40689b2d
|
||||
0x1e: 0x411111f0
|
||||
0x21: 0x04211020
|
||||
hdaudioC0D2
|
||||
vendor_name: Intel
|
||||
chip_name: Meteor Lake HDMI
|
||||
vendor_id: 0x8086281d
|
||||
subsystem_id: 0x80860101
|
||||
revision_id: 0x100000
|
||||
0x04: 0x18560010
|
||||
0x06: 0x18560010
|
||||
0x08: 0x18560010
|
||||
0x0a: 0x18560010
|
||||
0x0b: 0x18560010
|
||||
0x0c: 0x18560010
|
||||
0x0d: 0x18560010
|
||||
0x0e: 0x18560010
|
||||
0x0f: 0x18560010
|
||||
22
models/lemp13/coreboot.config
Normal file
22
models/lemp13/coreboot.config
Normal file
@ -0,0 +1,22 @@
|
||||
CONFIG_VENDOR_SYSTEM76=y
|
||||
CONFIG_BOARD_SYSTEM76_LEMP13=y
|
||||
CONFIG_CCACHE=y
|
||||
CONFIG_CONSOLE_SERIAL=n
|
||||
CONFIG_ADD_FSP_BINARIES=y
|
||||
CONFIG_FSP_FULL_FD=y
|
||||
CONFIG_FSP_FD_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/MeteorLakeFspBinPkg/Fsp.fd"
|
||||
CONFIG_FSP_HEADER_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/MeteorLakeFspBinPkg/Include"
|
||||
CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
|
||||
CONFIG_CPU_UCODE_BINARIES="$(FIRMWARE_OPEN_MODEL_DIR)/microcode.rom"
|
||||
CONFIG_HAVE_IFD_BIN=y
|
||||
CONFIG_HAVE_ME_BIN=y
|
||||
CONFIG_IFD_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/fd.rom"
|
||||
CONFIG_ME_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/me.rom"
|
||||
CONFIG_PAYLOAD_ELF=y
|
||||
CONFIG_PAYLOAD_FILE="$(FIRMWARE_OPEN_UEFIPAYLOAD)"
|
||||
CONFIG_POST_IO=n
|
||||
CONFIG_SMMSTORE=y
|
||||
CONFIG_SMMSTORE_V2=y
|
||||
CONFIG_USE_OPTION_TABLE=y
|
||||
CONFIG_VALIDATE_INTEL_DESCRIPTOR=y
|
||||
#CONFIG_CONSOLE_SYSTEM76_EC=y
|
||||
1
models/lemp13/ec.config
Normal file
1
models/lemp13/ec.config
Normal file
@ -0,0 +1 @@
|
||||
BOARD=system76/lemp13
|
||||
89
models/lemp13/ecspy.txt
Normal file
89
models/lemp13/ecspy.txt
Normal file
@ -0,0 +1,89 @@
|
||||
id 5570 rev 7
|
||||
A0: data 0 mirror 0 pot 0 control 82
|
||||
A1: data 1 mirror 1 pot 0 control 80
|
||||
A2: data 0 mirror 0 pot 0 control 00
|
||||
A3: data 1 mirror 1 pot 0 control 40
|
||||
A4: data 1 mirror 1 pot 0 control 44
|
||||
A5: data 0 mirror 0 pot 0 control 00
|
||||
A6: data 0 mirror 0 pot 0 control 00
|
||||
A7: data 0 mirror 0 pot 0 control 80
|
||||
B0: data 0 mirror 0 pot 0 control 84
|
||||
B1: data 1 mirror 1 pot 0 control 84
|
||||
B2: data 1 mirror 1 pot 0 control 80
|
||||
B3: data 1 mirror 1 pot 0 control 80
|
||||
B4: data 1 mirror 1 pot 0 control 40
|
||||
B5: data 1 mirror 1 pot 0 control 80
|
||||
B6: data 1 mirror 1 pot 0 control 44
|
||||
B7: data 1 mirror 1 pot 0 control 80
|
||||
C0: data 1 mirror 1 pot 0 control 80
|
||||
C1: data 0 mirror 0 pot 0 control 04
|
||||
C2: data 1 mirror 0 pot 0 control 04
|
||||
C3: data 0 mirror 0 pot 0 control 04
|
||||
C4: data 0 mirror 0 pot 0 control 84
|
||||
C5: data 0 mirror 0 pot 0 control 04
|
||||
C6: data 1 mirror 1 pot 0 control 80
|
||||
C7: data 1 mirror 1 pot 0 control 44
|
||||
D0: data 1 mirror 1 pot 0 control 40
|
||||
D1: data 1 mirror 1 pot 0 control 44
|
||||
D2: data 1 mirror 1 pot 0 control 00
|
||||
D3: data 1 mirror 1 pot 0 control 80
|
||||
D4: data 1 mirror 1 pot 0 control 40
|
||||
D5: data 1 mirror 1 pot 0 control 40
|
||||
D6: data 0 mirror 0 pot 0 control 02
|
||||
D7: data 0 mirror 0 pot 0 control 80
|
||||
E0: data 1 mirror 1 pot 0 control 04
|
||||
E1: data 1 mirror 1 pot 0 control 80
|
||||
E2: data 1 mirror 1 pot 0 control 80
|
||||
E3: data 1 mirror 1 pot 0 control 40
|
||||
E4: data 1 mirror 1 pot 0 control 40
|
||||
E5: data 1 mirror 1 pot 0 control 40
|
||||
E6: data 1 mirror 1 pot 0 control 80
|
||||
E7: data 1 mirror 1 pot 0 control 04
|
||||
F0: data 0 mirror 0 pot 0 control 44
|
||||
F1: data 1 mirror 1 pot 0 control 40
|
||||
F2: data 1 mirror 1 pot 0 control 44
|
||||
F3: data 1 mirror 1 pot 0 control 44
|
||||
F4: data 1 mirror 1 pot 0 control 04
|
||||
F5: data 1 mirror 1 pot 0 control 04
|
||||
F6: data 0 mirror 0 pot 0 control 00
|
||||
F7: data 1 mirror 1 pot 0 control 80
|
||||
G0: data 0 mirror 0 pot 0 control 80
|
||||
G1: data 1 mirror 1 pot 0 control 80
|
||||
G2: data 1 mirror 1 pot 0 control 80
|
||||
G3: data 0 mirror 0 pot 0 control 00
|
||||
G4: data 0 mirror 0 pot 0 control 00
|
||||
G5: data 0 mirror 0 pot 0 control 00
|
||||
G6: data 0 mirror 0 pot 0 control 40
|
||||
G7: data 0 mirror 0 pot 0 control 00
|
||||
H0: data 1 mirror 1 pot 0 control 80
|
||||
H1: data 1 mirror 1 pot 0 control 80
|
||||
H2: data 0 mirror 0 pot 0 control 44
|
||||
H3: data 1 mirror 1 pot 0 control 44
|
||||
H4: data 1 mirror 1 pot 0 control 44
|
||||
H5: data 0 mirror 0 pot 0 control 80
|
||||
H6: data 1 mirror 1 pot 0 control 80
|
||||
H7: data 1 mirror 1 pot 0 control 80
|
||||
I0: data 0 mirror 0 pot 0 control 00
|
||||
I1: data 0 mirror 0 pot 0 control 00
|
||||
I2: data 1 mirror 1 pot 0 control 84
|
||||
I3: data 0 mirror 0 pot 0 control 00
|
||||
I4: data 0 mirror 0 pot 0 control 00
|
||||
I5: data 1 mirror 1 pot 0 control 80
|
||||
I6: data 0 mirror 0 pot 0 control 00
|
||||
I7: data 0 mirror 0 pot 0 control 00
|
||||
J0: data 1 mirror 1 pot 0 control 80
|
||||
J1: data 1 mirror 1 pot 0 control 40
|
||||
J2: data 0 mirror 0 pot 0 control 00
|
||||
J3: data 1 mirror 1 pot 0 control 80
|
||||
J4: data 1 mirror 1 pot 0 control 40
|
||||
J5: data 1 mirror 1 pot 0 control 80
|
||||
J6: data 0 mirror 0 pot 0 control 44
|
||||
J7: data 0 mirror 0 pot 0 control 84
|
||||
M0: data 0 mirror 1 control 06
|
||||
M1: data 0 mirror 1 control 06
|
||||
M2: data 0 mirror 1 control 06
|
||||
M3: data 0 mirror 1 control 06
|
||||
M4: data 0 mirror 1 control 06
|
||||
M5: data 0 mirror 0 control 00
|
||||
M6: data 1 mirror 1 control 86
|
||||
M7: data 0 mirror 0 control 00
|
||||
9
models/lemp13/edk2.config
Normal file
9
models/lemp13/edk2.config
Normal file
@ -0,0 +1,9 @@
|
||||
BOOTLOADER=COREBOOT
|
||||
DISABLE_SERIAL_TERMINAL=TRUE
|
||||
PLATFORM_BOOT_TIMEOUT=2
|
||||
PS2_KEYBOARD_ENABLE=TRUE
|
||||
SECURE_BOOT_ENABLE=TRUE
|
||||
SERIAL_DRIVER_ENABLE=FALSE
|
||||
SHELL_TYPE=NONE
|
||||
TPM_ENABLE=TRUE
|
||||
#SYSTEM76_EC_LOGGING=TRUE
|
||||
BIN
models/lemp13/fd.rom
(Stored with Git LFS)
Normal file
BIN
models/lemp13/fd.rom
(Stored with Git LFS)
Normal file
Binary file not shown.
208
models/lemp13/gpio.c
Normal file
208
models/lemp13/gpio.c
Normal file
@ -0,0 +1,208 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <mainboard/gpio.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
static const struct pad_config gpio_table[] = {
|
||||
PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_A7, NONE),
|
||||
PAD_NC(GPP_A8, NONE),
|
||||
PAD_NC(GPP_A9, NONE),
|
||||
PAD_NC(GPP_A10, NONE),
|
||||
PAD_CFG_GPO(GPP_A11, 0, PLTRST),
|
||||
PAD_NC(GPP_A12, NONE),
|
||||
PAD_CFG_TERM_GPO(GPP_A13, 1, UP_20K, PLTRST),
|
||||
PAD_CFG_TERM_GPO(GPP_A14, 0, UP_20K, PLTRST),
|
||||
PAD_CFG_TERM_GPO(GPP_A15, 0, UP_20K, PLTRST),
|
||||
PAD_CFG_NF(GPP_A16, UP_20K, DEEP, NF1),
|
||||
_PAD_CFG_STRUCT(GPP_A17, 0x40100100, 0x0000),
|
||||
PAD_CFG_TERM_GPO(GPP_A18, 0, UP_20K, PLTRST),
|
||||
PAD_CFG_TERM_GPO(GPP_A19, 0, UP_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_A20, 0, NATIVE, DEEP),
|
||||
PAD_CFG_NF(GPP_A21, NATIVE, DEEP, NF1),
|
||||
_PAD_CFG_STRUCT(GPP_B0, 0x40100100, 0x0000),
|
||||
PAD_CFG_GPO(GPP_B1, 0, PLTRST),
|
||||
PAD_CFG_GPO(GPP_B2, 0, PLTRST),
|
||||
PAD_CFG_GPO(GPP_B3, 0, PLTRST),
|
||||
PAD_CFG_GPO(GPP_B4, 0, PLTRST),
|
||||
PAD_CFG_GPO(GPP_B5, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_B6, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B7, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_B8, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_B9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B10, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_B11, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B13, NONE, PLTRST, NF1),
|
||||
PAD_CFG_GPO(GPP_B14, 0, PLTRST),
|
||||
PAD_CFG_GPI(GPP_B15, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B16, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_B17, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_B18, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_B19, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_B20, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_B21, 0, PLTRST),
|
||||
PAD_CFG_GPI(GPP_B22, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_B23, 1, DEEP),
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C2, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_C3, 0, PLTRST),
|
||||
PAD_CFG_GPO(GPP_C4, 0, PLTRST),
|
||||
PAD_CFG_NF(GPP_C5, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C6, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_C7, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_C10, 0, PLTRST),
|
||||
PAD_CFG_NF(GPP_C11, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPP_C12, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPO(GPP_C13, 1, DEEP),
|
||||
PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_C17, NONE),
|
||||
PAD_NC(GPP_C18, NONE),
|
||||
PAD_NC(GPP_C19, NONE),
|
||||
PAD_CFG_GPO(GPP_C20, 0, PLTRST),
|
||||
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_C23, 0, PLTRST),
|
||||
PAD_CFG_GPO(GPP_D0, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_D1, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_D2, 1, PLTRST),
|
||||
PAD_NC(GPP_D3, NONE),
|
||||
PAD_CFG_GPO(GPP_D4, 0, PLTRST),
|
||||
PAD_CFG_GPO(GPP_D5, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_D6, 0, PLTRST),
|
||||
PAD_CFG_GPO(GPP_D7, 0, PLTRST),
|
||||
PAD_CFG_GPO(GPP_D8, 0, PLTRST),
|
||||
PAD_CFG_GPO(GPP_D9, 0, PLTRST),
|
||||
PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_D14, 0, PLTRST),
|
||||
PAD_CFG_GPO(GPP_D15, 0, PLTRST),
|
||||
PAD_CFG_GPO(GPP_D16, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_D18, NONE),
|
||||
PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D22, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D23, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_E0, 0, PLTRST),
|
||||
_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x1000),
|
||||
PAD_CFG_GPI(GPP_E2, NONE, DEEP),
|
||||
PAD_NC(GPP_E3, NONE),
|
||||
PAD_CFG_GPO(GPP_E4, 0, PLTRST),
|
||||
PAD_CFG_GPO(GPP_E5, 0, PLTRST),
|
||||
PAD_CFG_GPI(GPP_E6, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_E7, 0, PLTRST),
|
||||
PAD_CFG_GPO(GPP_E8, 0, PLTRST),
|
||||
PAD_CFG_GPI(GPP_E9, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_E10, 0, PLTRST),
|
||||
PAD_CFG_GPI(GPP_E11, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_E12, 0x84002200, 0x0000),
|
||||
_PAD_CFG_STRUCT(GPP_E13, 0x44002100, 0x0000),
|
||||
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_E15, 0, PLTRST),
|
||||
PAD_CFG_NF(GPP_E16, NONE, DEEP, NF2),
|
||||
PAD_CFG_GPO(GPP_E17, 0, PLTRST),
|
||||
PAD_NC(GPP_E18, NONE),
|
||||
PAD_NC(GPP_E19, NONE),
|
||||
PAD_NC(GPP_E20, NONE),
|
||||
PAD_NC(GPP_E21, NONE),
|
||||
PAD_CFG_TERM_GPO(GPP_E22, 0, DN_20K, PLTRST),
|
||||
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3),
|
||||
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F7, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F8, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_F9, NONE, DEEP),
|
||||
PAD_NC(GPP_F10, NONE),
|
||||
PAD_CFG_GPO(GPP_F11, 0, PLTRST),
|
||||
_PAD_CFG_STRUCT(GPP_F12, 0x44002300, 0x0000),
|
||||
_PAD_CFG_STRUCT(GPP_F13, 0x44002300, 0x0000),
|
||||
PAD_CFG_GPO(GPP_F14, 0, PLTRST),
|
||||
PAD_CFG_GPO(GPP_F15, 0, PLTRST),
|
||||
PAD_CFG_GPO(GPP_F16, 0, PLTRST),
|
||||
PAD_CFG_GPO(GPP_F17, 0, PLTRST),
|
||||
PAD_CFG_GPO(GPP_F18, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F19, 0, PLTRST),
|
||||
PAD_CFG_GPO(GPP_F20, 0, PLTRST),
|
||||
PAD_CFG_GPO(GPP_F21, 0, PLTRST),
|
||||
PAD_CFG_GPO(GPP_F22, 0, PLTRST),
|
||||
PAD_CFG_GPO(GPP_F23, 0, PLTRST),
|
||||
PAD_CFG_GPO(GPP_H0, 0, PLTRST),
|
||||
PAD_CFG_GPO(GPP_H1, 0, PLTRST),
|
||||
PAD_CFG_GPO(GPP_H2, 1, PLTRST),
|
||||
PAD_NC(GPP_H3, NONE),
|
||||
PAD_NC(GPP_H4, NONE),
|
||||
PAD_NC(GPP_H5, NONE),
|
||||
PAD_NC(GPP_H6, NONE),
|
||||
PAD_NC(GPP_H7, NONE),
|
||||
PAD_NC(GPP_H8, NONE),
|
||||
PAD_NC(GPP_H9, NONE),
|
||||
PAD_CFG_GPO(GPP_H10, 0, PLTRST),
|
||||
PAD_CFG_GPO(GPP_H11, 0, PLTRST),
|
||||
PAD_NC(GPP_H12, NONE),
|
||||
PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_H14, 0, PLTRST),
|
||||
PAD_CFG_GPO(GPP_H15, 0, PLTRST),
|
||||
PAD_CFG_GPO(GPP_H16, 0, PLTRST),
|
||||
PAD_CFG_GPO(GPP_H17, 0, PLTRST),
|
||||
PAD_NC(GPP_H18, NONE),
|
||||
PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_S0, 0, PLTRST),
|
||||
PAD_CFG_GPO(GPP_S1, 0, PLTRST),
|
||||
PAD_CFG_GPO(GPP_S2, 0, PLTRST),
|
||||
PAD_CFG_GPO(GPP_S3, 0, PLTRST),
|
||||
PAD_CFG_GPO(GPP_S4, 0, PLTRST),
|
||||
PAD_CFG_GPO(GPP_S5, 0, PLTRST),
|
||||
PAD_CFG_NF(GPP_S6, NONE, DEEP, NF3),
|
||||
PAD_CFG_NF(GPP_S7, NONE, DEEP, NF3),
|
||||
PAD_CFG_NF(GPP_V0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_V1, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_V2, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_V3, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_V4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_V5, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_V6, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_V7, NATIVE, DEEP),
|
||||
PAD_CFG_NF(GPP_V8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_V9, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_V12, NONE),
|
||||
PAD_CFG_NF(GPP_V13, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_V15, NONE, PLTRST, NF1),
|
||||
PAD_CFG_GPO(GPP_V16, 0, PLTRST),
|
||||
PAD_CFG_GPO(GPP_V17, 0, PLTRST),
|
||||
PAD_NC(GPP_V18, NONE),
|
||||
PAD_CFG_NF(GPP_V19, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_V20, NONE),
|
||||
PAD_NC(GPP_V21, NONE),
|
||||
PAD_NC(GPP_V22, NONE),
|
||||
PAD_NC(GPP_V23, NONE),
|
||||
};
|
||||
|
||||
void mainboard_configure_gpios(void)
|
||||
{
|
||||
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
|
||||
}
|
||||
42
models/lemp13/hda_verb.c
Normal file
42
models/lemp13/hda_verb.c
Normal file
@ -0,0 +1,42 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC245 */
|
||||
0x10ec0245, /* Vendor ID */
|
||||
0x15582624, /* Subsystem ID */
|
||||
13, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x15582624),
|
||||
AZALIA_RESET(1),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
|
||||
AZALIA_PIN_CFG(0, 0x13, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x17, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x40689b2d),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x21, 0x04211020),
|
||||
/* Intel, MeteorLakeHDMI */
|
||||
0x8086281d, /* Vendor ID */
|
||||
0x80860101, /* Subsystem ID */
|
||||
11, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(2, 0x80860101),
|
||||
AZALIA_RESET(1),
|
||||
AZALIA_PIN_CFG(2, 0x04, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x06, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x08, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0a, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0b, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0c, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0d, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0e, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0f, 0x18560010),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
BIN
models/lemp13/me.rom
(Stored with Git LFS)
Normal file
BIN
models/lemp13/me.rom
(Stored with Git LFS)
Normal file
Binary file not shown.
BIN
models/lemp13/microcode.rom
(Stored with Git LFS)
Normal file
BIN
models/lemp13/microcode.rom
(Stored with Git LFS)
Normal file
Binary file not shown.
BIN
models/lemp13/vbt.rom
(Stored with Git LFS)
Normal file
BIN
models/lemp13/vbt.rom
(Stored with Git LFS)
Normal file
Binary file not shown.
Loading…
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Reference in New Issue
Block a user