sravan/system76-firmware-open
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Update coreboot and darp6 config

Browse Source
This commit is contained in:
Jeremy Soller
2020-01-13 11:06:49 -07:00
parent 618023f3d8
commit 4a251d33e3
2 changed files with 7 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
coreboot

Submodule coreboot updated: 28dab93390...3b4db8f4a7

7
models/darp6/coreboot.config
View File

@ -114,7 +114,7 @@ CONFIG_MAX_REBOOT_CNT=3
CONFIG_OVERRIDE_DEVICETREE=""
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
CONFIG_FMDFILE=""
CONFIG_DCACHE_BSP_STACK_SIZE=0x20000
CONFIG_DCACHE_BSP_STACK_SIZE=0x20400
CONFIG_MMCONF_BASE_ADDRESS=0xe0000000
CONFIG_HAVE_INTEL_FIRMWARE=y
# CONFIG_POST_DEVICE is not set
@ -153,6 +153,7 @@ CONFIG_BOARD_SYSTEM76_DARP6=y
# CONFIG_BOARD_SYSTEM76_GALP2 is not set
# CONFIG_BOARD_SYSTEM76_GALP3 is not set
# CONFIG_BOARD_SYSTEM76_GALP3_B is not set
# CONFIG_BOARD_SYSTEM76_LEMP9 is not set
# CONFIG_BOARD_SYSTEM76_THELIO_B1 is not set
# CONFIG_BOARD_SYSTEM76_GALP3_C is not set
# CONFIG_BOARD_SYSTEM76_DARP5 is not set
@ -527,6 +528,10 @@ CONFIG_CARDBUS_PLUGIN_SUPPORT=y
# CONFIG_AZALIA_PLUGIN_SUPPORT is not set
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
CONFIG_PCIEXP_HOTPLUG=y
CONFIG_PCIEXP_HOTPLUG_BUSES=32
CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
CONFIG_PCIEXP_HOTPLUG_IO=0x2000
# CONFIG_EARLY_PCI_BRIDGE is not set
CONFIG_INTEL_GMA_HAVE_VBT=y
CONFIG_INTEL_GMA_ADD_VBT=y