diff --git a/coreboot b/coreboot
index f786129..5352c7b 160000
--- a/coreboot
+++ b/coreboot
@@ -1 +1 @@
-Subproject commit f7861291041eb9fafaddede561fb32d50863a7d2
+Subproject commit 5352c7b0b25544c8067ddff4c3258f35601a1f14
diff --git a/ec b/ec
index abc9b84..c1b7777 160000
--- a/ec
+++ b/ec
@@ -1 +1 @@
-Subproject commit abc9b843680780dd065f65f529fed974fbf059d0
+Subproject commit c1b7777a8b0dc4333c92ee140466c05adeba85cf
diff --git a/models/galp5/coreboot.config b/models/galp5/coreboot.config
index 1098be2..ccfa757 100644
--- a/models/galp5/coreboot.config
+++ b/models/galp5/coreboot.config
@@ -119,8 +119,8 @@ CONFIG_UART_FOR_CONSOLE=2
 CONFIG_CONSOLE_POST=y
 CONFIG_TPM_PIRQ=0x0
 # CONFIG_POST_DEVICE is not set
-CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
 # CONFIG_VBOOT is not set
+CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
 CONFIG_DCACHE_RAM_BASE=0xfef00000
 CONFIG_DCACHE_RAM_SIZE=0x80000
 CONFIG_DCACHE_BSP_STACK_SIZE=0x40400
@@ -211,7 +211,6 @@ CONFIG_SYSTEM_TYPE_LAPTOP=y
 # SoC
 #
 CONFIG_CPU_SPECIFIC_OPTIONS=y
-CONFIG_X86_RESET_VECTOR=0xfffffff0
 CONFIG_ROMSTAGE_ADDR=0x2000000
 CONFIG_VERSTAGE_ADDR=0x2000000
 CONFIG_RAMBASE=0xe00000
@@ -245,8 +244,8 @@ CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL=0x7fff
 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
 CONFIG_PCIEXP_ASPM=y
 CONFIG_PCIEXP_COMMON_CLOCK=y
-CONFIG_UART_PCI_ADDR=0x0
 CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=4
+CONFIG_UART_PCI_ADDR=0x0
 CONFIG_SOC_INTEL_TIGERLAKE=y
 CONFIG_CHIPSET_DEVICETREE="soc/intel/tigerlake/chipset.cb"
 CONFIG_VBT_DATA_SIZE_KB=9
@@ -552,6 +551,7 @@ CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 # CONFIG_AZALIA_PLUGIN_SUPPORT is not set
 CONFIG_PCIEXP_PLUGIN_SUPPORT=y
 CONFIG_PCI_ALLOW_BUS_MASTER=y
+CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
 CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
 CONFIG_PCIEXP_HOTPLUG=y
 # CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G is not set
diff --git a/models/lemp10/coreboot.config b/models/lemp10/coreboot.config
index 2fa3ba6..6531582 100644
--- a/models/lemp10/coreboot.config
+++ b/models/lemp10/coreboot.config
@@ -119,8 +119,8 @@ CONFIG_UART_FOR_CONSOLE=2
 CONFIG_CONSOLE_POST=y
 CONFIG_TPM_PIRQ=0x0
 # CONFIG_POST_DEVICE is not set
-CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
 # CONFIG_VBOOT is not set
+CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
 CONFIG_DCACHE_RAM_BASE=0xfef00000
 CONFIG_DCACHE_RAM_SIZE=0x80000
 CONFIG_DCACHE_BSP_STACK_SIZE=0x40400
@@ -211,7 +211,6 @@ CONFIG_SYSTEM_TYPE_LAPTOP=y
 # SoC
 #
 CONFIG_CPU_SPECIFIC_OPTIONS=y
-CONFIG_X86_RESET_VECTOR=0xfffffff0
 CONFIG_ROMSTAGE_ADDR=0x2000000
 CONFIG_VERSTAGE_ADDR=0x2000000
 CONFIG_RAMBASE=0xe00000
@@ -245,8 +244,8 @@ CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL=0x7fff
 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
 CONFIG_PCIEXP_ASPM=y
 CONFIG_PCIEXP_COMMON_CLOCK=y
-CONFIG_UART_PCI_ADDR=0x0
 CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=4
+CONFIG_UART_PCI_ADDR=0x0
 CONFIG_SOC_INTEL_TIGERLAKE=y
 CONFIG_CHIPSET_DEVICETREE="soc/intel/tigerlake/chipset.cb"
 CONFIG_VBT_DATA_SIZE_KB=9
@@ -552,6 +551,7 @@ CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 # CONFIG_AZALIA_PLUGIN_SUPPORT is not set
 CONFIG_PCIEXP_PLUGIN_SUPPORT=y
 CONFIG_PCI_ALLOW_BUS_MASTER=y
+CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
 CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
 CONFIG_PCIEXP_HOTPLUG=y
 # CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G is not set