coreboot: Rebase on 4.15

Rebase on upstream coreboot/coreboot@5622666396. The is slightly ahead
of the 4.15 tag, but includes all of our boards and most Intel SoC
changes we need.

We are now ~10 patches on top of upstream.

The following boards have been upstreamed:

- addw1
- addw2
- bonw14
- darp5
- darp6
- darp7
- galp2
- galp3-b
- galp3-c
- galp4
- galp5
- gaze14
- gaze15
- gaze16
- lemp10
- oryp5
- oryp6
- oryp7
- oryp8

The following drivers have been upstreamed:

- tas5825m

microcode:

- TGL-U boards have been updated to rev 0x9a from private repo
- TGL-H boards have been updated to rev 0x3c from private repo
- Remaining boards changed to use blobs from public repo

FSP:

- TGL changed to use A.0.51.31 from public repo

Signed-off-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
Tim Crawford
2021-12-21 10:32:37 -07:00
parent fb9d759338
commit 5b4dbd9c53
152 changed files with 50 additions and 66406 deletions

View File

@@ -1,9 +1,7 @@
CONFIG_VENDOR_SYSTEM76=y
CONFIG_BOARD_SYSTEM76_ORYP6=y
CONFIG_CCACHE=y
CONFIG_CONSOLE_SERIAL=n
CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
CONFIG_CPU_UCODE_BINARIES="$(FIRMWARE_OPEN_MODEL_DIR)/microcode.rom"
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
CONFIG_HAVE_IFD_BIN=y
CONFIG_HAVE_ME_BIN=y
CONFIG_IFD_BIN_PATH="$(FIRMWARE_OPEN_MODEL_DIR)/fd.rom"
@@ -15,7 +13,6 @@ CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x20000000
CONFIG_POST_IO=n
CONFIG_RUN_FSP_GOP=y
CONFIG_SMMSTORE=y
CONFIG_SUBSYSTEM_DEVICE_ID=0x50d3
CONFIG_SUBSYSTEM_VENDOR_ID=0x1558
CONFIG_USE_OPTION_TABLE=y
CONFIG_VALIDATE_INTEL_DESCRIPTOR=y
#CONFIG_CONSOLE_SYSTEM76_EC=y

BIN
models/oryp6/microcode.rom (Stored with Git LFS)

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