From 5d997d1c412c38838d58aeb700316e2a95006fba Mon Sep 17 00:00:00 2001
From: Tim Crawford <tcrawford@system76.com>
Date: Thu, 12 Oct 2023 11:58:39 -0600
Subject: [PATCH] coreboot: Fix OZ711LV2 LTR for galp5 3050 variant

Fix programming the LTR so that CPU can reach C-states deeper than C2.

Signed-off-by: Tim Crawford <tcrawford@system76.com>
---
 CHANGELOG.md | 1 +
 coreboot     | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/CHANGELOG.md b/CHANGELOG.md
index 4bfd2e6..d5d1690 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -9,6 +9,7 @@ features apply to your model and firmware version, see the
 ## unreleased
 
 - tgl-u: Fixed potential EC lock up during opportunistic suspend
+- galp5: Fixed CPU not going lower than C2 due to card reader LTR
 
 ## 2023-09-19
 
diff --git a/coreboot b/coreboot
index e86eb25..49d3764 160000
--- a/coreboot
+++ b/coreboot
@@ -1 +1 @@
-Subproject commit e86eb250cf26ac326da736fae1208f816727e47d
+Subproject commit 49d376482b76c6c9f127a97be28d90a82a6a5659