From 7291bc7d39cb7fa45fcdd8c96130f391681e5e39 Mon Sep 17 00:00:00 2001 From: Tim Crawford Date: Mon, 14 Nov 2022 12:57:49 -0700 Subject: [PATCH] coreboot: Disable SATA DevSlp on S0ix boards After changing EC detection of S0ix from CPU_C10_GATE# to SLP_S0#, DevSlp blocks S0ix entry. Disable it for now on TGL-U and ADL-P. Signed-off-by: Tim Crawford --- CHANGELOG.md | 4 +++- coreboot | 2 +- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 40ea6d0..25fbc81 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -4,12 +4,14 @@ Changes are identified by the date of the released firmware including them. If you are running System76 Open Firmware, opening the boot menu will show this date followed by an underscore and a short git revision. -## 2022-11-10 +## 2022-11-14 - lemp11: Added workaround to force S0ix entry on suspend - tgl-u: Removed CPU PCIe RP RTD3 config to fix suspend with certain drives - adl-p: Removed CPU PCIe RP RTD3 config to fix suspend with certain drives - adl-p: Fixed ACPI brightness controls on Windows 10 and Linux 6.1 +- adl-p: Disabled SATA DevSlp to fix S0ix entry +- tgl-u: Disabled SATA DevSlp to fix S0ix entry ## 2022-10-14 diff --git a/coreboot b/coreboot index 923476d..421b2ec 160000 --- a/coreboot +++ b/coreboot @@ -1 +1 @@ -Subproject commit 923476d15aa5722c624d9ddf3df7c1d82d11f3ca +Subproject commit 421b2ecbb0b273b01f4831720b6cbcab705d5e4c