models: Remove generated C files
These files are generated while running proprietary firmware, but once
they are added to coreboot they are no longer needed. They also quickly
become stale as the files are always changed in coreboot.
find models/ -name gpio.h -exec rm {} \;
find models/ -name hda_verb.c -exec rm {} \;
Signed-off-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
Tim Crawford
committed by
Jeremy Soller
Jeremy Soller
parent
e4960f163e
commit
77581d11fc
@ -1,245 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef MAINBOARD_GPIO_H
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#define MAINBOARD_GPIO_H
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#include <soc/gpe.h>
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#include <soc/gpio.h>
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#ifndef __ACPI__
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/* Pad configuration in ramstage. */
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static const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
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PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1),
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PAD_CFG_GPI(GPD2, NATIVE, PWROK),
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PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
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PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
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PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
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PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
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PAD_CFG_GPI(GPD7, NONE, PWROK),
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PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
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PAD_CFG_NF(GPD9, NONE, PWROK, NF1),
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_PAD_CFG_STRUCT(GPD10, 0x04000601, 0x0000),
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PAD_CFG_NF(GPD11, NONE, DEEP, NF1),
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PAD_CFG_TERM_GPO(GPP_A0, 0, NONE, DEEP),
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PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),
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PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),
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PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),
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PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),
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PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
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PAD_CFG_GPI(GPP_A7, NONE, DEEP),
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PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
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PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1),
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PAD_CFG_GPI(GPP_A11, UP_20K, DEEP),
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PAD_CFG_GPI(GPP_A12, NONE, DEEP),
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PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1),
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PAD_CFG_GPI(GPP_A16, DN_20K, DEEP),
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PAD_CFG_GPI(GPP_A17, NONE, DEEP),
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PAD_CFG_TERM_GPO(GPP_A18, 1, NONE, DEEP),
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PAD_CFG_GPI(GPP_A19, NONE, DEEP),
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PAD_CFG_TERM_GPO(GPP_A20, 1, NONE, DEEP),
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PAD_CFG_GPI(GPP_A21, NONE, DEEP),
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PAD_CFG_TERM_GPO(GPP_A22, 0, NONE, DEEP),
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PAD_CFG_GPI(GPP_A23, NONE, DEEP),
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PAD_CFG_GPI(GPP_B0, NONE, DEEP),
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PAD_CFG_GPI(GPP_B1, NONE, DEEP),
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PAD_CFG_GPI(GPP_B2, NONE, DEEP),
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_PAD_CFG_STRUCT(GPP_B3, 0x80100100, 0x0000),
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PAD_CFG_GPI(GPP_B4, NONE, DEEP),
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PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
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PAD_CFG_GPI(GPP_B6, NONE, DEEP),
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PAD_CFG_GPI(GPP_B7, NONE, DEEP),
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PAD_CFG_GPI(GPP_B8, NONE, DEEP),
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PAD_CFG_GPI(GPP_B9, NONE, DEEP),
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PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
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PAD_CFG_GPI(GPP_B11, NONE, DEEP),
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PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
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_PAD_CFG_STRUCT(GPP_B13, 0x44000601, 0x0000),
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PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
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PAD_CFG_GPI(GPP_B15, NONE, DEEP),
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PAD_CFG_GPI(GPP_B16, NONE, DEEP),
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PAD_CFG_GPI(GPP_B17, NONE, DEEP),
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PAD_CFG_GPI(GPP_B18, NONE, DEEP),
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PAD_CFG_GPI(GPP_B19, NONE, DEEP),
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PAD_CFG_GPI(GPP_B20, NONE, DEEP),
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PAD_CFG_GPI(GPP_B21, NONE, DEEP),
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PAD_CFG_GPI(GPP_B22, NONE, DEEP),
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PAD_CFG_GPI(GPP_B23, NONE, DEEP),
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PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
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_PAD_CFG_STRUCT(GPP_C2, 0x40880100, 0x0000),
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PAD_CFG_GPI(GPP_C3, NONE, DEEP),
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PAD_CFG_GPI(GPP_C4, NONE, DEEP),
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PAD_CFG_GPI(GPP_C5, NONE, DEEP),
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PAD_CFG_GPI(GPP_C6, NONE, DEEP),
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PAD_CFG_GPI(GPP_C7, NONE, DEEP),
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PAD_CFG_GPI(GPP_C8, NONE, DEEP),
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PAD_CFG_GPI(GPP_C9, NONE, DEEP),
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PAD_CFG_GPI(GPP_C10, NONE, DEEP),
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PAD_CFG_GPI(GPP_C11, NONE, DEEP),
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PAD_CFG_GPI(GPP_C12, NONE, DEEP),
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PAD_CFG_GPI(GPP_C13, NONE, DEEP),
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PAD_CFG_TERM_GPO(GPP_C14, 1, NONE, DEEP),
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PAD_CFG_GPI(GPP_C15, NONE, DEEP),
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PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1),
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PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1),
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PAD_CFG_NF(GPP_C18, NONE, PLTRST, NF1),
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PAD_CFG_NF(GPP_C19, NONE, PLTRST, NF1),
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PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1),
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PAD_CFG_GPI(GPP_D0, NONE, DEEP),
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PAD_CFG_GPI(GPP_D1, NONE, DEEP),
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PAD_CFG_GPI(GPP_D2, NONE, DEEP),
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PAD_CFG_GPI(GPP_D3, NONE, DEEP),
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PAD_CFG_GPI(GPP_D4, NONE, DEEP),
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PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3),
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PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3),
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PAD_CFG_GPI(GPP_D7, NONE, DEEP),
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PAD_CFG_GPI(GPP_D8, NONE, DEEP),
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PAD_CFG_GPI(GPP_D9, NONE, DEEP),
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PAD_CFG_GPI(GPP_D10, NONE, DEEP),
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PAD_CFG_GPI(GPP_D11, NONE, DEEP),
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PAD_CFG_GPI(GPP_D12, NONE, DEEP),
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PAD_CFG_GPI(GPP_D13, NONE, DEEP),
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PAD_CFG_GPI(GPP_D14, NONE, DEEP),
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PAD_CFG_GPI(GPP_D15, NONE, DEEP),
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PAD_CFG_GPI(GPP_D16, NONE, DEEP),
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PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
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PAD_CFG_GPI(GPP_D21, NONE, DEEP),
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PAD_CFG_GPI(GPP_D22, NONE, DEEP),
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PAD_CFG_GPI(GPP_D23, NONE, DEEP),
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PAD_CFG_GPI(GPP_E0, NONE, DEEP),
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PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1),
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PAD_CFG_GPI(GPP_E2, NONE, DEEP),
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PAD_CFG_GPI(GPP_E3, NONE, DEEP),
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PAD_CFG_GPI(GPP_E4, NONE, DEEP),
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PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
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PAD_CFG_TERM_GPO(GPP_E6, 1, NONE, DEEP),
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PAD_CFG_GPI(GPP_E7, NONE, DEEP),
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PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
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PAD_CFG_GPI(GPP_E9, NONE, DEEP),
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PAD_CFG_GPI(GPP_E10, NONE, DEEP),
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PAD_CFG_GPI(GPP_E11, NONE, DEEP),
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PAD_CFG_GPI(GPP_E12, NONE, DEEP),
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PAD_CFG_GPI(GPP_F0, NONE, DEEP),
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PAD_CFG_GPI(GPP_F1, NONE, DEEP),
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PAD_CFG_GPI(GPP_F2, NONE, DEEP),
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PAD_CFG_TERM_GPO(GPP_F3, 1, NONE, DEEP),
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PAD_CFG_TERM_GPO(GPP_F4, 1, NONE, DEEP),
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PAD_CFG_GPI(GPP_F5, NONE, DEEP),
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PAD_CFG_GPI(GPP_F6, NONE, DEEP),
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PAD_CFG_GPI(GPP_F7, NONE, DEEP),
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PAD_CFG_GPI(GPP_F8, NONE, DEEP),
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PAD_CFG_TERM_GPO(GPP_F9, 0, NONE, DEEP),
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PAD_CFG_GPI(GPP_F10, NONE, DEEP),
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PAD_CFG_GPI(GPP_F11, NONE, DEEP),
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PAD_CFG_GPI(GPP_F12, NONE, DEEP),
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PAD_CFG_GPI(GPP_F13, NONE, DEEP),
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PAD_CFG_GPI(GPP_F14, NONE, DEEP),
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PAD_CFG_GPI(GPP_F15, NONE, DEEP),
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PAD_CFG_GPI(GPP_F16, NONE, DEEP),
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PAD_CFG_GPI(GPP_F17, NONE, DEEP),
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PAD_CFG_GPI(GPP_F18, NONE, DEEP),
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PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
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PAD_CFG_TERM_GPO(GPP_F22, 0, NONE, DEEP),
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PAD_CFG_TERM_GPO(GPP_F23, 1, NONE, DEEP),
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PAD_CFG_GPI(GPP_G0, NONE, DEEP),
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PAD_CFG_GPI(GPP_G1, NONE, DEEP),
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PAD_CFG_GPI(GPP_G2, NONE, DEEP),
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PAD_CFG_GPI(GPP_G3, NONE, DEEP),
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PAD_CFG_GPI(GPP_G4, NONE, DEEP),
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PAD_CFG_GPI(GPP_G5, NONE, DEEP),
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PAD_CFG_GPI(GPP_G6, NONE, DEEP),
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PAD_CFG_GPI(GPP_G7, NONE, DEEP),
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PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
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PAD_CFG_GPI(GPP_H5, NONE, DEEP),
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PAD_CFG_TERM_GPO(GPP_H6, 1, NONE, DEEP),
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PAD_CFG_TERM_GPO(GPP_H7, 1, NONE, DEEP),
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PAD_CFG_GPI(GPP_H8, NONE, DEEP),
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PAD_CFG_GPI(GPP_H9, NONE, DEEP),
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PAD_CFG_GPI(GPP_H10, NONE, DEEP),
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PAD_CFG_GPI(GPP_H11, NONE, DEEP),
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PAD_CFG_GPI(GPP_H12, NONE, DEEP),
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PAD_CFG_GPI(GPP_H13, NONE, DEEP),
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PAD_CFG_GPI(GPP_H14, NONE, DEEP),
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PAD_CFG_GPI(GPP_H15, NONE, DEEP),
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_PAD_CFG_STRUCT(GPP_H16, 0x44000101, 0x0000),
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PAD_CFG_TERM_GPO(GPP_H17, 0, NONE, PLTRST),
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PAD_CFG_TERM_GPO(GPP_H18, 1, NONE, DEEP),
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PAD_CFG_TERM_GPO(GPP_H19, 1, NONE, DEEP),
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PAD_CFG_GPI(GPP_H20, NONE, DEEP),
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PAD_CFG_GPI(GPP_H21, NONE, DEEP),
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PAD_CFG_GPI(GPP_H22, NONE, DEEP),
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_PAD_CFG_STRUCT(GPP_H23, 0x82880100, 0x0000),
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_PAD_CFG_STRUCT(GPP_I0, 0x46080100, 0x0000),
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_PAD_CFG_STRUCT(GPP_I1, 0x46080100, 0x0000),
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_PAD_CFG_STRUCT(GPP_I2, 0x46080100, 0x0000),
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_PAD_CFG_STRUCT(GPP_I3, 0x46080100, 0x0000),
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PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1),
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PAD_CFG_TERM_GPO(GPP_I5, 1, NONE, DEEP),
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PAD_CFG_GPI(GPP_I6, NONE, DEEP),
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PAD_CFG_GPI(GPP_I7, NONE, DEEP),
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PAD_CFG_TERM_GPO(GPP_I8, 1, NONE, DEEP),
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PAD_CFG_TERM_GPO(GPP_I9, 1, NONE, DEEP),
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PAD_CFG_GPI(GPP_I10, NONE, DEEP),
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PAD_CFG_GPI(GPP_I11, NONE, DEEP),
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PAD_CFG_TERM_GPO(GPP_I12, 1, NONE, DEEP),
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PAD_CFG_GPI(GPP_I13, NONE, DEEP),
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PAD_CFG_GPI(GPP_I14, NONE, DEEP),
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PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1),
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PAD_CFG_TERM_GPO(GPP_J1, 1, NONE, DEEP),
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PAD_CFG_GPI(GPP_J2, NONE, DEEP),
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PAD_CFG_GPI(GPP_J3, NONE, DEEP),
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PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1),
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PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1),
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PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1),
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PAD_CFG_GPI(GPP_J10, NONE, DEEP),
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PAD_CFG_GPI(GPP_J11, DN_20K, DEEP),
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PAD_CFG_TERM_GPO(GPP_K0, 0, NONE, DEEP),
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PAD_CFG_TERM_GPO(GPP_K1, 0, NONE, DEEP),
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PAD_CFG_GPI(GPP_K2, NONE, DEEP),
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_PAD_CFG_STRUCT(GPP_K3, 0x40880100, 0x0000),
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PAD_CFG_GPI(GPP_K4, NONE, DEEP),
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PAD_CFG_GPI(GPP_K5, NONE, DEEP),
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_PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000),
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PAD_CFG_GPI(GPP_K7, NONE, DEEP),
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PAD_CFG_TERM_GPO(GPP_K8, 1, NONE, DEEP),
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PAD_CFG_GPI(GPP_K9, NONE, DEEP),
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PAD_CFG_GPI(GPP_K10, NONE, DEEP),
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PAD_CFG_GPI(GPP_K11, NONE, DEEP),
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PAD_CFG_TERM_GPO(GPP_K12, 1, NONE, DEEP),
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PAD_CFG_GPI(GPP_K13, NONE, DEEP),
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PAD_CFG_TERM_GPO(GPP_K14, 0, NONE, DEEP),
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_PAD_CFG_STRUCT(GPP_K15, 0x80100100, 0x0000),
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PAD_CFG_GPI(GPP_K16, NONE, DEEP),
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PAD_CFG_GPI(GPP_K17, NONE, DEEP),
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PAD_CFG_TERM_GPO(GPP_K18, 1, NONE, DEEP),
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_PAD_CFG_STRUCT(GPP_K19, 0x42800101, 0x0000),
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PAD_CFG_GPI(GPP_K20, NONE, DEEP),
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PAD_CFG_GPI(GPP_K21, NONE, DEEP),
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_PAD_CFG_STRUCT(GPP_K22, 0x44000101, 0x0000),
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PAD_CFG_GPI(GPP_K23, NONE, DEEP),
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};
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#endif
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#endif
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@ -1,43 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/azalia_device.h>
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const u32 cim_verb_data[] = {
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/* Realtek, ALC1220 */
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0x10ec1220, /* Vendor ID */
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0x155865d1, /* Subsystem ID */
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12, /* Number of entries */
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AZALIA_SUBVENDOR(0, 0x155865d1),
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AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
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AZALIA_PIN_CFG(0, 0x14, 0x0421101f),
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AZALIA_PIN_CFG(0, 0x15, 0x40000000),
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AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
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AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
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AZALIA_PIN_CFG(0, 0x18, 0x04a11040),
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AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
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AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
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AZALIA_PIN_CFG(0, 0x1b, 0x90170110),
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AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d),
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AZALIA_PIN_CFG(0, 0x1e, 0x04451150),
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/* Intel, KabylakeHDMI */
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0x8086280b, /* Vendor ID */
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0x80860101, /* Subsystem ID */
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4, /* Number of entries */
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AZALIA_SUBVENDOR(2, 0x80860101),
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AZALIA_PIN_CFG(2, 0x05, 0x18560010),
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AZALIA_PIN_CFG(2, 0x06, 0x18560010),
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AZALIA_PIN_CFG(2, 0x07, 0x18560010),
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/* Nvidia, GPU93HDMI/DP */
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0x10de0093, /* Vendor ID */
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0x155865d1, /* Subsystem ID */
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5, /* Number of entries */
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AZALIA_SUBVENDOR(0, 0x155865d1),
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AZALIA_PIN_CFG(0, 0x04, 0x185600f0),
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AZALIA_PIN_CFG(0, 0x05, 0x185600f0),
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AZALIA_PIN_CFG(0, 0x06, 0x185600f0),
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AZALIA_PIN_CFG(0, 0x07, 0x185600f0),
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};
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||||
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const u32 pc_beep_verbs[] = {};
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AZALIA_ARRAY_SIZES;
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@ -1,258 +0,0 @@
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/*
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||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2019 System76
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#ifndef __ACPI__
|
||||
|
||||
/* Pad configuration in ramstage. */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD2, NATIVE, PWROK),
|
||||
PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD7, NONE, PWROK),
|
||||
PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD9, NONE, PWROK, NF1),
|
||||
_PAD_CFG_STRUCT(GPD10, 0x04000601, 0x0000),
|
||||
PAD_CFG_NF(GPD11, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_A0, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_A7, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_A11, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A12, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
|
||||
_PAD_CFG_STRUCT(GPP_A14, 0x80800100, 0x0000),
|
||||
PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_A16, DN_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A17, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_A18, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A20, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_A21, 0x46080100, 0x0000),
|
||||
PAD_CFG_TERM_GPO(GPP_A22, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A23, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_B0, 0x42080100, 0x3000),
|
||||
PAD_CFG_GPI(GPP_B1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B2, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_B3, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B4, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_B6, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_B7, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B8, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B9, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_B11, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
_PAD_CFG_STRUCT(GPP_B13, 0x44000601, 0x0000),
|
||||
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_B15, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B17, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B18, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B19, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_B20, 0x42840101, 0x0000),
|
||||
PAD_CFG_GPI(GPP_B21, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B22, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B23, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_C2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C8, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C13, NONE, PLTRST),
|
||||
PAD_CFG_TERM_GPO(GPP_C14, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C15, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_C18, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_C19, NONE, PLTRST, NF1),
|
||||
PAD_CFG_GPI(GPP_C20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C21, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C22, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C23, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D4, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3),
|
||||
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3),
|
||||
PAD_CFG_GPI(GPP_D7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D8, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D14, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D15, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D16, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_D21, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D22, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D23, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E0, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E4, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_E6, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E7, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F2, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_F3, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F8, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_F9, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F14, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F15, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F17, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F18, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_F22, 1, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_F23, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G7, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_H4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H5, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_H6, 1, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_H7, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H8, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_H9, 0x40880100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_H10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H14, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H15, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_H16, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_H17, 0, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_H18, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_H19, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_H20, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H21, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H22, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_H23, 0x82880100, 0x0000),
|
||||
_PAD_CFG_STRUCT(GPP_I0, 0x46080100, 0x0000),
|
||||
_PAD_CFG_STRUCT(GPP_I1, 0x46080100, 0x0000),
|
||||
_PAD_CFG_STRUCT(GPP_I2, 0x46080100, 0x0000),
|
||||
_PAD_CFG_STRUCT(GPP_I3, 0x46080100, 0x0000),
|
||||
PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_I5, 0, UP_20K, PLTRST),
|
||||
PAD_CFG_GPI(GPP_I6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I7, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_I8, 1, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_I9, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I11, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_I12, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I14, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_J1, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_J2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_J3, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_J10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_J11, DN_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K0, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K1, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K2, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_K3, 0x40880100, 0x0000),
|
||||
_PAD_CFG_STRUCT(GPP_K4, 0x44000101, 0x0000),
|
||||
PAD_CFG_GPI(GPP_K5, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_K7, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K8, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K11, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K12, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K13, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K14, 0, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_K15, 0x80100100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_K16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K17, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K18, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K21, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K22, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K23, NONE, DEEP),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -1,43 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC1220 */
|
||||
0x10ec1220, /* Vendor ID */
|
||||
0x155865e1, /* Subsystem ID */
|
||||
12, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x155865e1),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x0421101f),
|
||||
AZALIA_PIN_CFG(0, 0x15, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x04a11040),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x04451150),
|
||||
/* Intel, KabylakeHDMI */
|
||||
0x8086280b, /* Vendor ID */
|
||||
0x80860101, /* Subsystem ID */
|
||||
4, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(2, 0x80860101),
|
||||
AZALIA_PIN_CFG(2, 0x05, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x06, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x07, 0x18560010),
|
||||
/* Nvidia, GPU92HDMI/DP */
|
||||
0x10de0092, /* Vendor ID */
|
||||
0x155865e1, /* Subsystem ID */
|
||||
5, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x155865e1),
|
||||
AZALIA_PIN_CFG(0, 0x04, 0x185600f0),
|
||||
AZALIA_PIN_CFG(0, 0x05, 0x185600f0),
|
||||
AZALIA_PIN_CFG(0, 0x06, 0x185600f0),
|
||||
AZALIA_PIN_CFG(0, 0x07, 0x185600f0),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
@ -1,272 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#ifndef __ACPI__
|
||||
|
||||
/* Pad configuration in ramstage. */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD2, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPO(GPD7, 0, PWROK),
|
||||
PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD9, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD11, NONE, PWROK, NF1),
|
||||
_PAD_CFG_STRUCT(GPD12, 0x04000300, 0x0000),
|
||||
PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A7, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A8, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A9, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A10, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A11, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A13, UP_20K, DEEP, NF1),
|
||||
PAD_NC(GPP_A14, NONE),
|
||||
_PAD_CFG_STRUCT(GPP_B0, 0x40100100, 0x0000),
|
||||
PAD_NC(GPP_B1, NONE),
|
||||
PAD_CFG_GPI(GPP_B2, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_B3, 1, DEEP),
|
||||
PAD_NC(GPP_B4, NONE),
|
||||
PAD_NC(GPP_B5, NONE),
|
||||
PAD_NC(GPP_B6, NONE),
|
||||
PAD_NC(GPP_B7, NONE),
|
||||
PAD_NC(GPP_B8, NONE),
|
||||
PAD_NC(GPP_B9, NONE),
|
||||
PAD_NC(GPP_B10, NONE),
|
||||
PAD_NC(GPP_B11, NONE),
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_B14, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_B15, NONE, DEEP),
|
||||
PAD_NC(GPP_B16, NONE),
|
||||
PAD_NC(GPP_B17, NONE),
|
||||
PAD_CFG_NF(GPP_B18, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPO(GPP_B19, 1, DEEP),
|
||||
PAD_CFG_NF(GPP_B20, DN_20K, DEEP, NF1),
|
||||
_PAD_CFG_STRUCT(GPP_B21, 0x42880100, 0x0000),
|
||||
PAD_CFG_GPO(GPP_B22, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_B23, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_C2, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF3),
|
||||
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF3),
|
||||
PAD_CFG_GPO(GPP_C5, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_C6, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_C7, NONE, DEEP, NF2),
|
||||
PAD_CFG_GPI(GPP_C8, NONE, DEEP),
|
||||
PAD_NC(GPP_C9, NONE),
|
||||
PAD_CFG_GPO(GPP_C10, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_C11, 1, DEEP),
|
||||
PAD_NC(GPP_C12, NONE),
|
||||
PAD_NC(GPP_C13, NONE),
|
||||
PAD_NC(GPP_C14, NONE),
|
||||
PAD_NC(GPP_C15, NONE),
|
||||
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_C20, NONE),
|
||||
PAD_NC(GPP_C21, NONE),
|
||||
PAD_NC(GPP_C22, NONE),
|
||||
PAD_NC(GPP_C23, NONE),
|
||||
PAD_NC(GPP_D0, NONE),
|
||||
PAD_NC(GPP_D1, NONE),
|
||||
PAD_NC(GPP_D2, NONE),
|
||||
PAD_NC(GPP_D3, NONE),
|
||||
PAD_NC(GPP_D4, NONE),
|
||||
PAD_NC(GPP_D5, NONE),
|
||||
PAD_NC(GPP_D6, NONE),
|
||||
PAD_NC(GPP_D7, NONE),
|
||||
PAD_NC(GPP_D8, NONE),
|
||||
PAD_CFG_NF(GPP_D9, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D10, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D14, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D15, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D16, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D17, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D18, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D19, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_E0, NONE),
|
||||
PAD_NC(GPP_E1, NONE),
|
||||
PAD_NC(GPP_E2, NONE),
|
||||
_PAD_CFG_STRUCT(GPP_E3, 0x42840101, 0x0000),
|
||||
PAD_NC(GPP_E4, NONE),
|
||||
PAD_NC(GPP_E5, NONE),
|
||||
PAD_NC(GPP_E6, NONE),
|
||||
_PAD_CFG_STRUCT(GPP_E7, 0x80100100, 0x0000),
|
||||
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_E13, NONE),
|
||||
PAD_NC(GPP_E14, NONE),
|
||||
PAD_CFG_GPO(GPP_E15, 0, DEEP),
|
||||
PAD_NC(GPP_E16, NONE),
|
||||
PAD_CFG_GPI(GPP_E17, DN_20K, DEEP),
|
||||
PAD_CFG_GPO(GPP_E18, 1, DEEP),
|
||||
PAD_NC(GPP_E19, NONE),
|
||||
PAD_NC(GPP_E20, NONE),
|
||||
PAD_NC(GPP_E21, NONE),
|
||||
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF2),
|
||||
PAD_NC(GPP_F1, NONE),
|
||||
PAD_CFG_GPO(GPP_F2, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_F3, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_F4, 1, PLTRST),
|
||||
PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_F6, NONE),
|
||||
PAD_CFG_GPI(GPP_F7, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_F8, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_F9, 1, DEEP),
|
||||
PAD_NC(GPP_F10, NONE),
|
||||
PAD_NC(GPP_F11, NONE),
|
||||
PAD_NC(GPP_F12, NONE),
|
||||
PAD_NC(GPP_F13, NONE),
|
||||
PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_F15, NONE, DEEP),
|
||||
PAD_NC(GPP_F16, NONE),
|
||||
PAD_CFG_GPI(GPP_F17, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_F18, 0, PLTRST),
|
||||
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_F22, NONE),
|
||||
PAD_NC(GPP_F23, NONE),
|
||||
PAD_CFG_GPI(GPP_G0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G1, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_G2, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_G3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G4, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_G6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G7, NONE, DEEP),
|
||||
PAD_NC(GPP_H0, NONE),
|
||||
PAD_CFG_GPI(GPP_H1, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_H3, NONE),
|
||||
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H10, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_H11, NONE, PLTRST, NF1),
|
||||
PAD_CFG_GPO(GPP_H12, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_H13, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_H14, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_H15, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_H16, NONE, PLTRST, NF1),
|
||||
PAD_CFG_GPO(GPP_H17, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_H18, 0, DEEP),
|
||||
PAD_NC(GPP_H19, NONE),
|
||||
PAD_NC(GPP_H20, NONE),
|
||||
PAD_CFG_GPO(GPP_H21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H22, 0, DEEP),
|
||||
PAD_NC(GPP_H23, NONE),
|
||||
PAD_CFG_GPI(GPP_I0, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1),
|
||||
_PAD_CFG_STRUCT(GPP_I2, 0x86800100, 0x0000),
|
||||
PAD_CFG_NF(GPP_I3, NONE, DEEP, NF1),
|
||||
_PAD_CFG_STRUCT(GPP_I4, 0x86800100, 0x0000),
|
||||
PAD_CFG_GPO(GPP_I5, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_I6, 0, DEEP),
|
||||
PAD_NC(GPP_I7, NONE),
|
||||
PAD_CFG_GPO(GPP_I8, 0, DEEP),
|
||||
PAD_NC(GPP_I9, NONE),
|
||||
PAD_NC(GPP_I10, NONE),
|
||||
PAD_CFG_NF(GPP_I11, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_I12, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_I13, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_I14, NONE, PLTRST, NF1),
|
||||
PAD_NC(GPP_I15, NONE),
|
||||
PAD_NC(GPP_I16, NONE),
|
||||
PAD_NC(GPP_I17, NONE),
|
||||
PAD_CFG_GPO(GPP_I18, 0, DEEP),
|
||||
PAD_NC(GPP_I19, NONE),
|
||||
PAD_NC(GPP_I20, NONE),
|
||||
PAD_NC(GPP_I21, NONE),
|
||||
PAD_CFG_GPO(GPP_I22, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J1, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_J8, NONE),
|
||||
PAD_NC(GPP_J9, NONE),
|
||||
PAD_CFG_NF(GPP_J10, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J11, DN_20K, DEEP, NF1),
|
||||
_PAD_CFG_STRUCT(GPP_K0, 0x42800100, 0x0000),
|
||||
PAD_NC(GPP_K1, NONE),
|
||||
PAD_NC(GPP_K2, NONE),
|
||||
PAD_CFG_GPO(GPP_K3, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_K4, 0, PWROK),
|
||||
PAD_NC(GPP_K5, NONE),
|
||||
PAD_CFG_NF(GPP_K6, UP_20K, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_K7, DN_20K, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_K8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_K9, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_K10, UP_20K, DEEP, NF2),
|
||||
PAD_NC(GPP_K11, NONE),
|
||||
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_R5, NONE),
|
||||
PAD_NC(GPP_R6, NONE),
|
||||
PAD_NC(GPP_R7, NONE),
|
||||
PAD_CFG_GPI(GPP_R8, NONE, PLTRST),
|
||||
PAD_CFG_NF(GPP_R9, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_R10, NONE),
|
||||
PAD_NC(GPP_R11, NONE),
|
||||
PAD_NC(GPP_R12, NONE),
|
||||
PAD_NC(GPP_R13, NONE),
|
||||
PAD_NC(GPP_R14, NONE),
|
||||
PAD_NC(GPP_R15, NONE),
|
||||
PAD_CFG_GPO(GPP_R16, 1, DEEP),
|
||||
PAD_NC(GPP_R17, NONE),
|
||||
PAD_NC(GPP_R18, NONE),
|
||||
PAD_NC(GPP_R19, NONE),
|
||||
PAD_NC(GPP_R20, NONE),
|
||||
PAD_CFG_GPO(GPP_R21, 0, DEEP),
|
||||
PAD_NC(GPP_S0, NONE),
|
||||
PAD_NC(GPP_S1, NONE),
|
||||
PAD_NC(GPP_S2, NONE),
|
||||
PAD_NC(GPP_S3, NONE),
|
||||
PAD_NC(GPP_S4, NONE),
|
||||
PAD_NC(GPP_S5, NONE),
|
||||
PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -1,48 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC256 */
|
||||
0x10ec0256, /* Vendor ID */
|
||||
0x1558a671, /* Subsystem ID */
|
||||
11, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x1558a671),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
|
||||
AZALIA_PIN_CFG(0, 0x13, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x02a11040),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x41700001),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x21, 0x02211020),
|
||||
/* Intel, RaptorlakeHDMI */
|
||||
0x80862818, /* Vendor ID */
|
||||
0x80860101, /* Subsystem ID */
|
||||
10, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(2, 0x80860101),
|
||||
AZALIA_PIN_CFG(2, 0x04, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x06, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x08, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0a, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0b, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0c, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0d, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0e, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0f, 0x18560010),
|
||||
/* Nvidia, GenericHDMI */
|
||||
0x10de00a6, /* Vendor ID */
|
||||
0x10de0000, /* Subsystem ID */
|
||||
5, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x10de0000),
|
||||
AZALIA_PIN_CFG(0, 0x04, 0x185600f0),
|
||||
AZALIA_PIN_CFG(0, 0x05, 0x585600f0),
|
||||
AZALIA_PIN_CFG(0, 0x06, 0x185600f0),
|
||||
AZALIA_PIN_CFG(0, 0x07, 0x585600f0),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
@ -1,245 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#ifndef __ACPI__
|
||||
|
||||
/* Pad configuration in ramstage. */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD2, NATIVE, PWROK),
|
||||
PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD6, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_GPI(GPD7, UP_20K, PWROK),
|
||||
PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD11, UP_20K, PWROK),
|
||||
PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A10, UP_20K, DEEP, NF1),
|
||||
_PAD_CFG_STRUCT(GPP_A11, 0x80100100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_A12, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A13, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A14, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A15, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_A17, UP_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_A18, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A19, UP_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_A20, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A21, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A22, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A23, UP_20K, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_B0, 0x42080100, 0x3000),
|
||||
PAD_CFG_GPI(GPP_B1, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_B3, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B4, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_B7, UP_20K, PLTRST),
|
||||
PAD_CFG_GPI(GPP_B8, UP_20K, PLTRST),
|
||||
PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_B10, UP_20K, PLTRST),
|
||||
PAD_CFG_TERM_GPO(GPP_B11, 1, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_B15, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_B16, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_B17, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_B18, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_B19, UP_20K, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_B20, 0x42040100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_B21, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_B22, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_C2, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_C8, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_C9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C10, DN_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_C11, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C12, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_C13, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_C14, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_C15, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_C18, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_C19, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_C20, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_C21, NONE, PLTRST, NF1),
|
||||
PAD_CFG_GPI(GPP_C22, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_C23, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D0, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D1, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D2, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D3, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D4, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3),
|
||||
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3),
|
||||
PAD_CFG_NF(GPP_D7, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_D8, NONE, PLTRST, NF1),
|
||||
PAD_CFG_GPI(GPP_D9, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D10, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D11, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D12, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D13, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D14, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D15, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D16, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_D17, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D18, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D19, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D20, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_D21, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D22, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D23, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_E0, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E2, NONE, DEEP, NF2),
|
||||
PAD_CFG_GPI(GPP_E3, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_E4, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1),
|
||||
_PAD_CFG_STRUCT(GPP_E7, 0x80800100, 0x0000),
|
||||
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E9, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_E10, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_E11, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_E12, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_F2, 0, UP_20K, PLTRST),
|
||||
PAD_CFG_NF(GPP_F3, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_F7, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F8, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F9, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F10, UP_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_F11, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F12, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F13, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_F14, NONE, DEEP, NF2),
|
||||
PAD_CFG_GPI(GPP_F15, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F16, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F17, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F18, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F19, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F20, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F21, UP_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_F22, 1, UP_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_F23, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G0, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_G1, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_G2, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_G3, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_G4, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_G5, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_G6, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_G7, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_H3, NONE, PLTRST),
|
||||
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_H5, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_H6, NONE, PLTRST),
|
||||
PAD_CFG_TERM_GPO(GPP_H7, 0, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H10, NONE, PLTRST, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_H11, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H12, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H13, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H14, UP_20K, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_H15, 0x40880100, 0x3000),
|
||||
PAD_CFG_GPI(GPP_H16, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H17, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H18, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H19, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H20, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H21, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H22, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H23, UP_20K, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_I0, 0x46080100, 0x0000),
|
||||
_PAD_CFG_STRUCT(GPP_I1, 0x46080100, 0x0000),
|
||||
_PAD_CFG_STRUCT(GPP_I2, 0x46080100, 0x0000),
|
||||
_PAD_CFG_STRUCT(GPP_I3, 0x46080100, 0x0000),
|
||||
PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_I5, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I6, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_I7, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_I8, UP_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_I9, 1, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_I10, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I11, UP_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_I12, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_I13, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I14, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J1, NONE, DEEP, NF2),
|
||||
PAD_CFG_GPI(GPP_J2, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_J3, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J9, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_J10, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_J11, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K0, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K1, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K2, UP_20K, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_K3, 0x80880100, 0x3000),
|
||||
PAD_CFG_GPI(GPP_K4, UP_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K5, 0, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_K7, UP_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K8, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K9, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K10, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K11, UP_20K, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_K12, 0x82880100, 0x3000),
|
||||
PAD_CFG_GPI(GPP_K13, UP_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K14, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K15, UP_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K16, 0, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K17, UP_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K18, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K19, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K20, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K21, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K22, 0, TODO_0x2800, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K23, 0, NONE, PLTRST),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -1,272 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#ifndef __ACPI__
|
||||
|
||||
/* Pad configuration in ramstage. */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),
|
||||
_PAD_CFG_STRUCT(GPD2, 0x42880100, 0x0000),
|
||||
PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPI(GPD7, NONE, PWROK),
|
||||
PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPO(GPD9, 0, PWROK),
|
||||
PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPO(GPD11, 0, DEEP),
|
||||
PAD_CFG_GPO(GPD12, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_A7, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A8, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A9, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_A11, UP_20K, DEEP),
|
||||
PAD_CFG_GPO(GPP_A12, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A13, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A14, 0, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_B0, 0x82900100, 0x0000),
|
||||
PAD_CFG_GPO(GPP_B1, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_B2, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_B3, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_B4, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B5, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B6, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B7, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B8, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B9, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B10, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B11, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_B15, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B16, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B17, 1, PWROK),
|
||||
PAD_CFG_NF(GPP_B18, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPO(GPP_B19, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_B20, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B22, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_B23, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_C2, NONE, PLTRST),
|
||||
PAD_CFG_GPO(GPP_C3, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_C4, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_C6, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_C7, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_C8, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_C9, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_C10, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_C11, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_C12, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_C13, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_C14, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_C15, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_C20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C21, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_C22, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_C23, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D0, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D1, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D2, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D3, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D4, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D5, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D6, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D7, 0, DEEP),
|
||||
PAD_NC(GPP_D8, NONE),
|
||||
PAD_CFG_NF(GPP_D9, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D10, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D14, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D15, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D16, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D17, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D18, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D19, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_E0, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E1, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E2, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E3, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E4, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E5, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E6, 0, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_E7, 0x80100100, 0x0000),
|
||||
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_E9, NONE),
|
||||
PAD_NC(GPP_E10, NONE),
|
||||
PAD_NC(GPP_E11, NONE),
|
||||
PAD_NC(GPP_E12, NONE),
|
||||
PAD_CFG_GPO(GPP_E13, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E14, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E15, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E16, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E17, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E18, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_E19, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E20, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F0, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F1, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F2, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F3, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F4, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F5, 0, PLTRST),
|
||||
PAD_CFG_GPO(GPP_F6, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F7, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_F8, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_F9, 0x42880100, 0x0000),
|
||||
PAD_CFG_GPO(GPP_F10, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F11, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F12, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F13, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F14, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_F15, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_F16, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F17, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F18, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_F22, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_F23, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_G0, 0, PWROK),
|
||||
PAD_CFG_GPI(GPP_G1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G2, DN_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_G3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G4, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_G6, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_G7, 0x42800100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_H0, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_H1, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_H2, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_H6, NONE),
|
||||
PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_H12, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_H15, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H16, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_H17, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_H18, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_H19, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H20, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H21, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_H22, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_H23, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_I0, 0, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_I1, 0x86880100, 0x0000),
|
||||
_PAD_CFG_STRUCT(GPP_I2, 0x86880100, 0x0000),
|
||||
_PAD_CFG_STRUCT(GPP_I3, 0x86880100, 0x0000),
|
||||
_PAD_CFG_STRUCT(GPP_I4, 0x86880100, 0x0000),
|
||||
PAD_CFG_GPO(GPP_I5, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_I6, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_I7, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_I8, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_I9, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_I10, 0, DEEP),
|
||||
PAD_NC(GPP_I11, NONE),
|
||||
PAD_NC(GPP_I12, NONE),
|
||||
PAD_NC(GPP_I13, NONE),
|
||||
PAD_NC(GPP_I14, NONE),
|
||||
PAD_CFG_GPO(GPP_I15, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_I16, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_I17, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_I18, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_I19, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_I20, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_I21, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_I22, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J1, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_J8, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_J9, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_J10, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_J11, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_K0, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_K1, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_K2, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_K3, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_K4, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_K5, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_K6, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_K7, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_K8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_K9, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_K10, NONE, DEEP, NF2),
|
||||
PAD_CFG_GPO(GPP_K11, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_R5, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_R6, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_R7, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_R8, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_R9, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_R10, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_R11, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_R12, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_R13, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_R14, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_R15, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_R16, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_R17, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_R18, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_R19, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_R20, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_R21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S0, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S1, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S2, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S3, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S4, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S5, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S6, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S7, 0, DEEP),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -1,49 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC1220 */
|
||||
0x10ec1220, /* Vendor ID */
|
||||
0x15583702, /* Subsystem ID */
|
||||
12, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x15583702),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x0421101f),
|
||||
AZALIA_PIN_CFG(0, 0x15, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x04a11040),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x04451150),
|
||||
/* Intel, RaptorlakeHDMI */
|
||||
0x80862818, /* Vendor ID */
|
||||
0x80860101, /* Subsystem ID */
|
||||
10, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(2, 0x80860101),
|
||||
AZALIA_PIN_CFG(2, 0x04, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x06, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x08, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0a, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0b, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0c, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0d, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0e, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0f, 0x18560010),
|
||||
/* Nvidia, GenericHDMI */
|
||||
0x10de00a5, /* Vendor ID */
|
||||
0x10de0000, /* Subsystem ID */
|
||||
5, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x10de0000),
|
||||
AZALIA_PIN_CFG(0, 0x04, 0x585600f0),
|
||||
AZALIA_PIN_CFG(0, 0x05, 0x185600f0),
|
||||
AZALIA_PIN_CFG(0, 0x06, 0x185600f0),
|
||||
AZALIA_PIN_CFG(0, 0x07, 0x185600f0),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
@ -1,218 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2019 System76
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#ifndef __ACPI__
|
||||
|
||||
/* Pad configuration in ramstage. */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
PAD_CFG_GPI(GPD0, NONE, PWROK),
|
||||
PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD2, NATIVE, PWROK),
|
||||
PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD7, NONE, PWROK),
|
||||
PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD9, NONE, PWROK),
|
||||
PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD11, NONE, PWROK),
|
||||
PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_A7, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_A11, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A12, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_A16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A17, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A18, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A21, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_A22, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A23, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B6, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_B11, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_B15, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B17, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B18, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B21, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B22, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B23, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_C2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C8, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_C9, 0x84800100, 0x3000),
|
||||
PAD_CFG_TERM_GPO(GPP_C10, 0, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_C11, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_C12, 1, NONE, PLTRST),
|
||||
PAD_CFG_TERM_GPO(GPP_C13, 1, NONE, PLTRST),
|
||||
PAD_CFG_TERM_GPO(GPP_C14, 0, NONE, PLTRST),
|
||||
PAD_CFG_TERM_GPO(GPP_C15, 1, UP_20K, PLTRST),
|
||||
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_C18, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C21, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C22, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_C23, 0x80100100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_D0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D7, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_D8, 1, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_D9, 0x40880100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_D10, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_D11, 0x40880100, 0x3000),
|
||||
PAD_CFG_GPI(GPP_D12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D14, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D15, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_D16, 1, NONE, PWROK),
|
||||
PAD_CFG_GPI(GPP_D17, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D18, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_D21, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D22, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D23, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E1, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E2, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E5, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E7, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E12, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E15, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_E16, 0x80880100, 0x0000),
|
||||
PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E22, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E23, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_F1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F3, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F7, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_F10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F14, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F15, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F17, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F18, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F21, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F22, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F23, DN_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_G0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H0, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3),
|
||||
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3),
|
||||
PAD_CFG_GPI(GPP_H3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H8, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H14, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H15, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H17, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_H19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H21, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_H22, 1, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_H23, NONE, DEEP),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -1,218 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2019 System76
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#ifndef __ACPI__
|
||||
|
||||
/* Pad configuration in ramstage. */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
PAD_CFG_GPI(GPD0, NONE, PWROK),
|
||||
PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD2, NATIVE, PWROK),
|
||||
PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD7, NONE, PWROK),
|
||||
PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD9, NONE, PWROK),
|
||||
PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD11, NONE, PWROK),
|
||||
PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_A7, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_A11, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A12, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_A16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A17, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A18, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A21, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_A22, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A23, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B6, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_B11, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_B15, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B17, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B18, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B21, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B22, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B23, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_C2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C8, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_C9, 0x84800100, 0x3000),
|
||||
PAD_CFG_TERM_GPO(GPP_C10, 0, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_C11, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_C12, 1, NONE, PLTRST),
|
||||
PAD_CFG_TERM_GPO(GPP_C13, 1, NONE, PLTRST),
|
||||
PAD_CFG_TERM_GPO(GPP_C14, 0, NONE, PLTRST),
|
||||
PAD_CFG_TERM_GPO(GPP_C15, 0, UP_20K, PLTRST),
|
||||
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_C18, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C21, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C22, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_C23, 0x80100100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_D0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D7, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_D8, 1, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_D9, 0x40880100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_D10, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_D11, 0x40880100, 0x3000),
|
||||
PAD_CFG_GPI(GPP_D12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D14, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_D15, 0, NONE, PLTRST),
|
||||
PAD_CFG_TERM_GPO(GPP_D16, 1, NONE, PWROK),
|
||||
PAD_CFG_GPI(GPP_D17, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D18, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_D21, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D22, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D23, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E1, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E2, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E5, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E7, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E12, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E15, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_E16, 0x80880100, 0x0000),
|
||||
PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E22, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E23, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_F1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F3, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F7, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_F10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F14, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F15, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F17, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F18, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F21, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F22, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F23, DN_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_G0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H0, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3),
|
||||
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3),
|
||||
PAD_CFG_GPI(GPP_H3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H8, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H14, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H15, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H17, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_H19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H21, NONE, DEEP),
|
||||
PAD_NC(GPP_H22, NONE),
|
||||
PAD_CFG_GPI(GPP_H23, NONE, DEEP),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -1,213 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#ifndef __ACPI__
|
||||
|
||||
/* Pad configuration in ramstage. */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),
|
||||
PAD_CFG_GPI(GPD2, NONE, PWROK),
|
||||
PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPD7, 1, NONE, PWROK),
|
||||
PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
|
||||
PAD_CFG_TERM_GPO(GPD9, 0, NONE, PWROK),
|
||||
PAD_CFG_NF(GPD10, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD11, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_A7, NONE),
|
||||
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_A9, NONE, DEEP, NF3),
|
||||
PAD_NC(GPP_A10, NONE),
|
||||
PAD_NC(GPP_A11, NONE),
|
||||
PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_A13, 1, NONE, PLTRST),
|
||||
PAD_NC(GPP_A14, NONE),
|
||||
PAD_NC(GPP_A15, NONE),
|
||||
PAD_NC(GPP_A16, NONE),
|
||||
PAD_NC(GPP_A17, NONE),
|
||||
PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_A19, NONE),
|
||||
PAD_NC(GPP_A20, NONE),
|
||||
PAD_NC(GPP_A21, NONE),
|
||||
PAD_NC(GPP_A22, NONE),
|
||||
PAD_CFG_TERM_GPO(GPP_A23, 0, NONE, PLTRST),
|
||||
PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_B2, UP_20K, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_B3, 0x80800100, 0x0000),
|
||||
PAD_NC(GPP_B4, NONE),
|
||||
PAD_NC(GPP_B5, NONE),
|
||||
PAD_NC(GPP_B6, NONE),
|
||||
PAD_NC(GPP_B7, NONE),
|
||||
PAD_CFG_TERM_GPO(GPP_B8, 1, NONE, DEEP),
|
||||
PAD_NC(GPP_B9, NONE),
|
||||
PAD_NC(GPP_B10, NONE),
|
||||
PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_B14, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_B15, 1, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_B16, 0x44000301, 0x0000),
|
||||
PAD_NC(GPP_B17, NONE),
|
||||
PAD_NC(GPP_B18, NONE),
|
||||
PAD_NC(GPP_B19, NONE),
|
||||
PAD_NC(GPP_B20, NONE),
|
||||
PAD_NC(GPP_B21, NONE),
|
||||
PAD_NC(GPP_B22, NONE),
|
||||
PAD_CFG_TERM_GPO(GPP_B23, 0, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_C2, NONE),
|
||||
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_C5, NONE),
|
||||
PAD_CFG_NF(GPP_C6, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPP_C7, NONE, PWROK, NF1),
|
||||
PAD_NC(GPP_C8, NONE),
|
||||
PAD_NC(GPP_C9, NONE),
|
||||
PAD_NC(GPP_C10, NONE),
|
||||
PAD_NC(GPP_C11, NONE),
|
||||
PAD_NC(GPP_C12, NONE),
|
||||
PAD_NC(GPP_C13, NONE),
|
||||
_PAD_CFG_STRUCT(GPP_C14, 0x40100100, 0x3000),
|
||||
PAD_NC(GPP_C15, NONE),
|
||||
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_C20, NONE),
|
||||
PAD_NC(GPP_C21, NONE),
|
||||
PAD_CFG_TERM_GPO(GPP_C22, 1, NONE, PLTRST),
|
||||
_PAD_CFG_STRUCT(GPP_C23, 0x40880100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_D0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_D1, 1, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_D2, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_D3, NONE, PLTRST),
|
||||
PAD_NC(GPP_D4, NONE),
|
||||
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_D9, NONE),
|
||||
PAD_NC(GPP_D10, NONE),
|
||||
PAD_CFG_GPI(GPP_D11, DN_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D12, DN_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_D13, 1, NONE, PLTRST),
|
||||
PAD_CFG_TERM_GPO(GPP_D14, 1, NONE, PLTRST),
|
||||
PAD_NC(GPP_D15, NONE),
|
||||
PAD_NC(GPP_D16, NONE),
|
||||
PAD_NC(GPP_D17, NONE),
|
||||
PAD_NC(GPP_D18, NONE),
|
||||
PAD_NC(GPP_D19, NONE),
|
||||
PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_E1, 0, NONE, PLTRST),
|
||||
_PAD_CFG_STRUCT(GPP_E2, 0x40880100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_E3, DN_20K, DEEP),
|
||||
PAD_NC(GPP_E4, NONE),
|
||||
PAD_NC(GPP_E5, NONE),
|
||||
PAD_NC(GPP_E6, NONE),
|
||||
_PAD_CFG_STRUCT(GPP_E7, 0x82840100, 0x0000),
|
||||
PAD_NC(GPP_E8, NONE),
|
||||
PAD_NC(GPP_E9, NONE),
|
||||
PAD_NC(GPP_E10, NONE),
|
||||
PAD_NC(GPP_E11, NONE),
|
||||
PAD_NC(GPP_E12, NONE),
|
||||
PAD_NC(GPP_E13, NONE),
|
||||
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_E15, NONE),
|
||||
PAD_CFG_GPI(GPP_E16, DN_20K, DEEP),
|
||||
PAD_NC(GPP_E17, NONE),
|
||||
PAD_NC(GPP_E18, NATIVE),
|
||||
PAD_NC(GPP_E19, NATIVE),
|
||||
PAD_NC(GPP_E20, NONE),
|
||||
PAD_NC(GPP_E21, NONE),
|
||||
PAD_NC(GPP_E22, NONE),
|
||||
PAD_NC(GPP_E23, NONE),
|
||||
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
|
||||
PAD_NC(GPP_F4, NONE),
|
||||
PAD_NC(GPP_F5, NONE),
|
||||
PAD_NC(GPP_F6, NONE),
|
||||
PAD_CFG_TERM_GPO(GPP_F7, 1, NONE, DEEP),
|
||||
PAD_NC(GPP_F8, NONE),
|
||||
PAD_CFG_TERM_GPO(GPP_F9, 1, NONE, DEEP),
|
||||
PAD_NC(GPP_F10, NONE),
|
||||
PAD_NC(GPP_F11, NONE),
|
||||
PAD_NC(GPP_F12, NONE),
|
||||
PAD_NC(GPP_F13, NONE),
|
||||
PAD_NC(GPP_F14, NONE),
|
||||
PAD_NC(GPP_F15, NONE),
|
||||
PAD_NC(GPP_F16, NONE),
|
||||
PAD_CFG_GPI(GPP_F17, NONE, PLTRST),
|
||||
PAD_NC(GPP_F18, NONE),
|
||||
PAD_NC(GPP_F19, NONE),
|
||||
PAD_NC(GPP_F20, NONE),
|
||||
PAD_CFG_GPI(GPP_F21, DN_20K, DEEP),
|
||||
PAD_NC(GPP_F22, NONE),
|
||||
PAD_NC(GPP_F23, NONE),
|
||||
PAD_CFG_TERM_GPO(GPP_H0, 1, NONE, PLTRST),
|
||||
PAD_NC(GPP_H1, NONE),
|
||||
PAD_NC(GPP_H2, NONE),
|
||||
PAD_CFG_GPI(GPP_H3, DN_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_H6, NONE),
|
||||
PAD_NC(GPP_H7, NONE),
|
||||
PAD_CFG_GPI(GPP_H8, DN_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H9, DN_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_H11, NONE),
|
||||
PAD_NC(GPP_H12, NONE),
|
||||
PAD_NC(GPP_H13, NONE),
|
||||
PAD_NC(GPP_H14, NONE),
|
||||
PAD_NC(GPP_H15, NONE),
|
||||
PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_H19, NONE),
|
||||
PAD_NC(GPP_H20, NONE),
|
||||
PAD_NC(GPP_H21, NONE),
|
||||
PAD_NC(GPP_H22, NONE),
|
||||
PAD_NC(GPP_H23, NONE),
|
||||
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_R5, NONE),
|
||||
PAD_NC(GPP_R6, NONE),
|
||||
PAD_NC(GPP_R7, NONE),
|
||||
PAD_NC(GPP_S0, NONE),
|
||||
PAD_NC(GPP_S1, NONE),
|
||||
PAD_NC(GPP_S2, NONE),
|
||||
PAD_NC(GPP_S3, NONE),
|
||||
PAD_NC(GPP_S4, NONE),
|
||||
PAD_NC(GPP_S5, NONE),
|
||||
PAD_NC(GPP_S6, NONE),
|
||||
PAD_NC(GPP_S7, NONE),
|
||||
PAD_NC(GPP_T2, NONE),
|
||||
PAD_NC(GPP_T3, NONE),
|
||||
PAD_CFG_TERM_GPO(GPP_U4, 0, NONE, PLTRST),
|
||||
PAD_CFG_TERM_GPO(GPP_U5, 1, NONE, PLTRST),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -1,40 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC293 */
|
||||
0x10ec0293, /* Vendor ID */
|
||||
0x155851a1, /* Subsystem ID */
|
||||
12, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x155851a1),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
|
||||
AZALIA_PIN_CFG(0, 0x13, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x15, 0x02211020),
|
||||
AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x40738205),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
|
||||
/* Intel, TigerlakeHDMI */
|
||||
0x80862812, /* Vendor ID */
|
||||
0x80860101, /* Subsystem ID */
|
||||
10, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(2, 0x80860101),
|
||||
AZALIA_PIN_CFG(2, 0x04, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x06, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x08, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0a, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0b, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0c, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0d, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0e, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0f, 0x18560010),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
@ -1,211 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#ifndef __ACPI__
|
||||
|
||||
/* Pad configuration in ramstage. */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPI(GPD7, NONE, PWROK),
|
||||
PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPO(GPD9, 0, PWROK),
|
||||
PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD11, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_A6, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A7, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_A8, 1, PLTRST),
|
||||
PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_A11, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_A13, 1, PLTRST),
|
||||
PAD_CFG_GPI(GPP_A14, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A15, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_A17, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_A19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A21, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A22, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_A23, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_B2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B8, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B10, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_B15, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_B16, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_B17, 1, PLTRST),
|
||||
PAD_CFG_GPI(GPP_B18, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B21, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B22, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B23, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_C2, 1, PLTRST),
|
||||
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_C5, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_C8, NONE),
|
||||
PAD_NC(GPP_C9, NONE),
|
||||
PAD_NC(GPP_C10, NONE),
|
||||
PAD_NC(GPP_C11, NONE),
|
||||
PAD_NC(GPP_C12, NONE),
|
||||
PAD_NC(GPP_C13, NONE),
|
||||
PAD_NC(GPP_C14, NONE),
|
||||
PAD_NC(GPP_C15, NONE),
|
||||
PAD_NC(GPP_C16, NONE),
|
||||
PAD_NC(GPP_C17, NONE),
|
||||
PAD_NC(GPP_C18, NONE),
|
||||
PAD_NC(GPP_C19, NONE),
|
||||
PAD_NC(GPP_C20, NONE),
|
||||
PAD_NC(GPP_C21, NONE),
|
||||
PAD_NC(GPP_C22, NONE),
|
||||
PAD_NC(GPP_C23, NONE),
|
||||
PAD_CFG_GPO(GPP_D0, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_D1, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_D2, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_D3, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_D4, 1, DEEP),
|
||||
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_D6, 1, DEEP),
|
||||
PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_D8, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D9, NATIVE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D10, NATIVE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D11, NATIVE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D12, NATIVE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D13, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_D14, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_D15, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_D16, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_D17, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D18, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E0, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000),
|
||||
PAD_CFG_GPI(GPP_E2, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_E3, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_E4, 0, PLTRST),
|
||||
PAD_CFG_GPI(GPP_E5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E8, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E11, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_E12, 0x40100100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_E13, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E15, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E17, NONE, DEEP),
|
||||
PAD_NC(GPP_E18, NATIVE),
|
||||
PAD_NC(GPP_E19, NATIVE),
|
||||
PAD_CFG_GPI(GPP_E20, NATIVE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E21, NATIVE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E22, DN_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_E23, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_F7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F8, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F14, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F15, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F16, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_F17, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_F18, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_F20, 1, PLTRST),
|
||||
PAD_CFG_GPI(GPP_F21, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_H0, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_H1, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_H2, 1, PLTRST),
|
||||
PAD_CFG_GPI(GPP_H3, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2),
|
||||
PAD_CFG_GPI(GPP_H10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H11, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_H12, 0x44001500, 0x0000),
|
||||
PAD_CFG_GPI(GPP_H13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H14, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_H16, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_H20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H21, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H22, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_R5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_S0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_S1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_S2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_S3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_S4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_S5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_S6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_S7, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_T2, DN_20K, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_T3, DN_20K, DEEP, NF2),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -1,39 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC256 */
|
||||
0x10ec0256, /* Vendor ID */
|
||||
0x15587716, /* Subsystem ID */
|
||||
11, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x15587716),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
|
||||
AZALIA_PIN_CFG(0, 0x13, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x41700001),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x21, 0x02211020),
|
||||
/* Intel, Alderlake-PHDMI */
|
||||
0x8086281c, /* Vendor ID */
|
||||
0x80860101, /* Subsystem ID */
|
||||
10, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(2, 0x80860101),
|
||||
AZALIA_PIN_CFG(2, 0x04, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x06, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x08, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0a, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0b, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0c, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0d, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0e, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0f, 0x18560010),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
@ -1,211 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#ifndef __ACPI__
|
||||
|
||||
/* Pad configuration in ramstage. */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPI(GPD7, NONE, PWROK),
|
||||
PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPO(GPD9, 0, PWROK),
|
||||
PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD11, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_A6, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A7, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A8, 1, PLTRST),
|
||||
PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_A11, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A12, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A13, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_A14, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A15, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_A17, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_A19, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A20, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A22, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_A23, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_B2, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B3, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B4, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B5, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B6, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B7, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B8, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B9, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B10, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_B15, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B16, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_B17, 1, PLTRST),
|
||||
PAD_CFG_GPI(GPP_B18, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_B19, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B20, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B22, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_B23, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_C2, 1, PLTRST),
|
||||
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_C5, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_C8, NONE),
|
||||
PAD_NC(GPP_C9, NONE),
|
||||
PAD_NC(GPP_C10, NONE),
|
||||
PAD_NC(GPP_C11, NONE),
|
||||
PAD_NC(GPP_C12, NONE),
|
||||
PAD_NC(GPP_C13, NONE),
|
||||
PAD_NC(GPP_C14, NONE),
|
||||
PAD_NC(GPP_C15, NONE),
|
||||
PAD_NC(GPP_C16, NONE),
|
||||
PAD_NC(GPP_C17, NONE),
|
||||
PAD_NC(GPP_C18, NONE),
|
||||
PAD_NC(GPP_C19, NONE),
|
||||
PAD_NC(GPP_C20, NONE),
|
||||
PAD_NC(GPP_C21, NONE),
|
||||
PAD_NC(GPP_C22, NONE),
|
||||
PAD_NC(GPP_C23, NONE),
|
||||
PAD_CFG_GPO(GPP_D0, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_D1, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_D2, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_D3, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_D4, 1, DEEP),
|
||||
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_D6, 1, DEEP),
|
||||
PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_D8, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D9, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D10, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_D11, NATIVE, DEEP),
|
||||
PAD_CFG_GPO(GPP_D12, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_D13, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_D14, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_D15, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D16, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_D17, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D18, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_D19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E0, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000),
|
||||
PAD_CFG_GPO(GPP_E2, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E3, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_E4, 0, PLTRST),
|
||||
PAD_CFG_GPI(GPP_E5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E6, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_E7, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_E8, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E11, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_E12, 0x40100100, 0x0000),
|
||||
PAD_CFG_GPO(GPP_E13, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_E15, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_E16, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_E17, 0, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_E18, 0x44001700, 0x3c00),
|
||||
_PAD_CFG_STRUCT(GPP_E19, 0x44001600, 0x3c00),
|
||||
PAD_CFG_GPO(GPP_E20, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E22, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E23, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_F7, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_F8, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F9, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_F10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F11, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_F12, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F13, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_F14, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F15, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_F16, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F17, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_F18, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_F20, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_F21, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_H0, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_H1, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_H2, 1, PLTRST),
|
||||
PAD_CFG_GPI(GPP_H3, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2),
|
||||
PAD_CFG_GPI(GPP_H10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H11, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_H12, 0x44001500, 0x0000),
|
||||
PAD_CFG_GPO(GPP_H13, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H14, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_H16, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_H20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H21, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H22, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_R5, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3),
|
||||
PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3),
|
||||
PAD_CFG_GPO(GPP_S0, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S1, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S2, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S3, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S4, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S5, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S6, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S7, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_T2, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_T3, 0, DEEP),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -1,39 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC256 */
|
||||
0x10ec0256, /* Vendor ID */
|
||||
0x155851b1, /* Subsystem ID */
|
||||
11, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x155851b1),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
|
||||
AZALIA_PIN_CFG(0, 0x13, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x41700001),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x21, 0x02211020),
|
||||
/* Intel, Raptorlake-PHDMI */
|
||||
0x8086281f, /* Vendor ID */
|
||||
0x80860101, /* Subsystem ID */
|
||||
10, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(2, 0x80860101),
|
||||
AZALIA_PIN_CFG(2, 0x04, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x06, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x08, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0a, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0b, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0c, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0d, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0e, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0f, 0x18560010),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
@ -1,218 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2019 System76
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#ifndef __ACPI__
|
||||
|
||||
/* Pad configuration in ramstage. */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
PAD_CFG_GPI(GPD0, NONE, PWROK),
|
||||
PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD2, NATIVE, PWROK),
|
||||
PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD7, NONE, PWROK),
|
||||
PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD9, NONE, PWROK),
|
||||
PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD11, NONE, PWROK),
|
||||
PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_A7, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_A11, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A12, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_A16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A17, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A18, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A21, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_A22, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A23, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B6, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_B11, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_B15, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B17, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B18, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B21, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B22, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B23, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_C2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C8, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_C9, 0x82880100, 0x3000),
|
||||
PAD_CFG_TERM_GPO(GPP_C10, 0, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_C11, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_C12, 1, NONE, PLTRST),
|
||||
PAD_CFG_TERM_GPO(GPP_C13, 1, NONE, PLTRST),
|
||||
PAD_CFG_TERM_GPO(GPP_C14, 0, NONE, PLTRST),
|
||||
PAD_CFG_TERM_GPO(GPP_C15, 1, UP_20K, PLTRST),
|
||||
PAD_CFG_GPI(GPP_C16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C17, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C18, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C21, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C22, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C23, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D7, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_D8, 1, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_D9, 0x40880100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_D10, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_D11, 0x40880100, 0x3000),
|
||||
PAD_CFG_GPI(GPP_D12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D14, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D15, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_D16, 1, NONE, PWROK),
|
||||
PAD_CFG_GPI(GPP_D17, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D18, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_D21, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D22, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D23, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E1, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E2, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E5, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E7, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E12, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E15, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_E16, 0x80880100, 0x0000),
|
||||
PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E22, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E23, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_F1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F3, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F7, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_F10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F14, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F15, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F17, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F18, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F21, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F22, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F23, DN_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_G0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H0, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3),
|
||||
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3),
|
||||
PAD_CFG_GPI(GPP_H3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H8, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H14, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H15, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H17, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_H19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H21, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_H22, 1, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_H23, NONE, DEEP),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -1,218 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2019 System76
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#ifndef __ACPI__
|
||||
|
||||
/* Pad configuration in ramstage. */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
PAD_CFG_GPI(GPD0, NONE, PWROK),
|
||||
PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD2, NATIVE, PWROK),
|
||||
PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD7, NONE, PWROK),
|
||||
PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD9, NONE, PWROK),
|
||||
PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD11, NONE, PWROK),
|
||||
PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_A7, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_A11, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A12, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_A16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A17, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A18, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A21, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_A22, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A23, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B6, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_B11, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_B15, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B17, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B18, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B21, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B22, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B23, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_C2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C8, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_C9, 0x84800100, 0x3000),
|
||||
PAD_CFG_TERM_GPO(GPP_C10, 0, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_C11, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_C12, 1, NONE, PLTRST),
|
||||
PAD_CFG_TERM_GPO(GPP_C13, 1, NONE, PLTRST),
|
||||
PAD_CFG_TERM_GPO(GPP_C14, 0, NONE, PLTRST),
|
||||
PAD_CFG_TERM_GPO(GPP_C15, 0, UP_20K, PLTRST),
|
||||
PAD_CFG_GPI(GPP_C16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C17, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C18, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C21, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C22, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C23, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D7, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_D8, 1, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_D9, 0x40880100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_D10, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_D11, 0x40880100, 0x3000),
|
||||
PAD_CFG_GPI(GPP_D12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D14, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_D15, 0, NONE, PLTRST),
|
||||
PAD_CFG_TERM_GPO(GPP_D16, 1, NONE, PWROK),
|
||||
PAD_CFG_GPI(GPP_D17, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D18, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_D21, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D22, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D23, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E1, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E2, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E5, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E7, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E12, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E15, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_E16, 0x80880100, 0x0000),
|
||||
PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E22, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E23, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_F1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F3, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F7, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_F10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F14, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F15, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F17, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F18, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F21, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F22, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F23, DN_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_G0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H0, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3),
|
||||
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3),
|
||||
PAD_CFG_GPI(GPP_H3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H8, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H14, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H15, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H17, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_H19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H21, NONE, DEEP),
|
||||
PAD_NC(GPP_H22, NONE),
|
||||
PAD_CFG_GPI(GPP_H23, NONE, DEEP),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -1,213 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#ifndef __ACPI__
|
||||
|
||||
/* Pad configuration in ramstage. */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),
|
||||
PAD_CFG_GPI(GPD2, NONE, PWROK),
|
||||
PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPD7, 1, NONE, PWROK),
|
||||
PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
|
||||
PAD_CFG_TERM_GPO(GPD9, 0, NONE, PWROK),
|
||||
PAD_CFG_NF(GPD10, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD11, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_A7, NONE),
|
||||
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_A9, NONE, DEEP, NF3),
|
||||
PAD_NC(GPP_A10, NONE),
|
||||
PAD_NC(GPP_A11, NONE),
|
||||
PAD_NC(GPP_A12, NONE),
|
||||
PAD_CFG_TERM_GPO(GPP_A13, 1, NONE, PLTRST),
|
||||
PAD_NC(GPP_A14, NONE),
|
||||
PAD_NC(GPP_A15, NONE),
|
||||
PAD_NC(GPP_A16, NONE),
|
||||
PAD_NC(GPP_A17, NONE),
|
||||
PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_A19, NONE),
|
||||
PAD_NC(GPP_A20, NONE),
|
||||
PAD_NC(GPP_A21, NONE),
|
||||
PAD_NC(GPP_A22, NONE),
|
||||
PAD_CFG_TERM_GPO(GPP_A23, 0, NONE, PLTRST),
|
||||
PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_B2, UP_20K, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_B3, 0x80800100, 0x0000),
|
||||
PAD_NC(GPP_B4, NONE),
|
||||
PAD_NC(GPP_B5, NONE),
|
||||
PAD_NC(GPP_B6, NONE),
|
||||
PAD_NC(GPP_B7, NONE),
|
||||
PAD_CFG_TERM_GPO(GPP_B8, 1, NONE, DEEP),
|
||||
PAD_NC(GPP_B9, NONE),
|
||||
PAD_NC(GPP_B10, NONE),
|
||||
PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_B14, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_B15, 1, NONE, DEEP),
|
||||
PAD_NC(GPP_B16, NONE),
|
||||
PAD_NC(GPP_B17, NONE),
|
||||
PAD_NC(GPP_B18, NONE),
|
||||
PAD_NC(GPP_B19, NONE),
|
||||
PAD_NC(GPP_B20, NONE),
|
||||
PAD_NC(GPP_B21, NONE),
|
||||
PAD_NC(GPP_B22, NONE),
|
||||
PAD_CFG_TERM_GPO(GPP_B23, 0, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_C2, NONE),
|
||||
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_C5, NONE),
|
||||
PAD_CFG_NF(GPP_C6, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPP_C7, NONE, PWROK, NF1),
|
||||
PAD_NC(GPP_C8, NONE),
|
||||
PAD_NC(GPP_C9, NONE),
|
||||
PAD_NC(GPP_C10, NONE),
|
||||
PAD_NC(GPP_C11, NONE),
|
||||
PAD_NC(GPP_C12, NONE),
|
||||
PAD_NC(GPP_C13, NONE),
|
||||
_PAD_CFG_STRUCT(GPP_C14, 0x40100100, 0x3000),
|
||||
PAD_NC(GPP_C15, NONE),
|
||||
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_C20, NONE),
|
||||
PAD_NC(GPP_C21, NONE),
|
||||
PAD_CFG_TERM_GPO(GPP_C22, 1, NONE, PLTRST),
|
||||
_PAD_CFG_STRUCT(GPP_C23, 0x40880100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_D0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_D1, 1, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_D2, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_D3, NONE, PLTRST),
|
||||
PAD_NC(GPP_D4, NONE),
|
||||
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_D9, NONE),
|
||||
PAD_NC(GPP_D10, NONE),
|
||||
PAD_CFG_GPI(GPP_D11, DN_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D12, DN_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_D13, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_D14, 1, NONE, PLTRST),
|
||||
PAD_NC(GPP_D15, NONE),
|
||||
PAD_NC(GPP_D16, NONE),
|
||||
PAD_CFG_GPI(GPP_D17, DN_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D18, DN_20K, DEEP),
|
||||
PAD_NC(GPP_D19, NONE),
|
||||
PAD_NC(GPP_E0, NONE),
|
||||
PAD_CFG_TERM_GPO(GPP_E1, 0, NONE, PLTRST),
|
||||
_PAD_CFG_STRUCT(GPP_E2, 0x40880100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_E3, DN_20K, DEEP),
|
||||
PAD_NC(GPP_E4, NONE),
|
||||
PAD_NC(GPP_E5, NONE),
|
||||
PAD_NC(GPP_E6, NONE),
|
||||
_PAD_CFG_STRUCT(GPP_E7, 0x82840100, 0x0000),
|
||||
PAD_NC(GPP_E8, NONE),
|
||||
PAD_NC(GPP_E9, NONE),
|
||||
PAD_NC(GPP_E10, NONE),
|
||||
PAD_NC(GPP_E11, NONE),
|
||||
PAD_NC(GPP_E12, NONE),
|
||||
PAD_NC(GPP_E13, NONE),
|
||||
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_E15, NONE),
|
||||
PAD_CFG_GPI(GPP_E16, DN_20K, DEEP),
|
||||
PAD_NC(GPP_E17, NONE),
|
||||
PAD_NC(GPP_E18, NATIVE),
|
||||
PAD_NC(GPP_E19, NATIVE),
|
||||
PAD_NC(GPP_E20, NONE),
|
||||
PAD_NC(GPP_E21, NONE),
|
||||
PAD_NC(GPP_E22, NONE),
|
||||
PAD_NC(GPP_E23, NONE),
|
||||
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
|
||||
PAD_NC(GPP_F4, NONE),
|
||||
PAD_NC(GPP_F5, NONE),
|
||||
PAD_NC(GPP_F6, NONE),
|
||||
PAD_CFG_TERM_GPO(GPP_F7, 1, NONE, DEEP),
|
||||
PAD_NC(GPP_F8, NONE),
|
||||
PAD_CFG_TERM_GPO(GPP_F9, 1, NONE, DEEP),
|
||||
PAD_NC(GPP_F10, NONE),
|
||||
PAD_NC(GPP_F11, NONE),
|
||||
PAD_NC(GPP_F12, NONE),
|
||||
PAD_NC(GPP_F13, NONE),
|
||||
PAD_NC(GPP_F14, NONE),
|
||||
PAD_NC(GPP_F15, NONE),
|
||||
PAD_NC(GPP_F16, NONE),
|
||||
PAD_CFG_GPI(GPP_F17, NONE, PLTRST),
|
||||
PAD_NC(GPP_F18, NONE),
|
||||
PAD_NC(GPP_F19, NONE),
|
||||
PAD_NC(GPP_F20, NONE),
|
||||
PAD_CFG_GPI(GPP_F21, DN_20K, DEEP),
|
||||
PAD_NC(GPP_F22, NONE),
|
||||
PAD_NC(GPP_F23, NONE),
|
||||
PAD_CFG_TERM_GPO(GPP_H0, 1, NONE, PLTRST),
|
||||
PAD_NC(GPP_H1, NONE),
|
||||
PAD_NC(GPP_H2, NONE),
|
||||
PAD_CFG_GPI(GPP_H3, DN_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_H6, NONE),
|
||||
PAD_NC(GPP_H7, NONE),
|
||||
PAD_CFG_GPI(GPP_H8, DN_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H9, DN_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_H11, NONE),
|
||||
PAD_NC(GPP_H12, NONE),
|
||||
PAD_NC(GPP_H13, NONE),
|
||||
PAD_NC(GPP_H14, NONE),
|
||||
PAD_NC(GPP_H15, NONE),
|
||||
PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_H19, NONE),
|
||||
PAD_NC(GPP_H20, NONE),
|
||||
PAD_NC(GPP_H21, NONE),
|
||||
PAD_NC(GPP_H22, NONE),
|
||||
PAD_NC(GPP_H23, NONE),
|
||||
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_R5, NONE),
|
||||
PAD_NC(GPP_R6, NONE),
|
||||
PAD_NC(GPP_R7, NONE),
|
||||
PAD_NC(GPP_S0, NONE),
|
||||
PAD_NC(GPP_S1, NONE),
|
||||
PAD_NC(GPP_S2, NONE),
|
||||
PAD_NC(GPP_S3, NONE),
|
||||
PAD_NC(GPP_S4, NONE),
|
||||
PAD_NC(GPP_S5, NONE),
|
||||
PAD_NC(GPP_S6, NONE),
|
||||
PAD_NC(GPP_S7, NONE),
|
||||
PAD_NC(GPP_T2, NONE),
|
||||
PAD_NC(GPP_T3, NONE),
|
||||
PAD_CFG_TERM_GPO(GPP_U4, 1, NONE, PLTRST),
|
||||
PAD_CFG_TERM_GPO(GPP_U5, 1, NONE, PLTRST),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -1,40 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC293 */
|
||||
0x10ec0293, /* Vendor ID */
|
||||
0x15584018, /* Subsystem ID */
|
||||
12, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x15584018),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
|
||||
AZALIA_PIN_CFG(0, 0x13, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x15, 0x02211020),
|
||||
AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x41748245),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
|
||||
/* Intel, TigerlakeHDMI */
|
||||
0x80862812, /* Vendor ID */
|
||||
0x80860101, /* Subsystem ID */
|
||||
10, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(2, 0x80860101),
|
||||
AZALIA_PIN_CFG(2, 0x04, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x06, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x08, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0a, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0b, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0c, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0d, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0e, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0f, 0x18560010),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
@ -1,211 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#ifndef __ACPI__
|
||||
|
||||
/* Pad configuration in ramstage. */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),
|
||||
PAD_CFG_GPI(GPD2, NATIVE, PWROK),
|
||||
PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPI(GPD7, NONE, PWROK),
|
||||
PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD11, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_A6, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A7, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A8, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_A11, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_A12, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_A13, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_A14, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_A15, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
|
||||
_PAD_CFG_STRUCT(GPP_A17, 0x80800100, 0x0000),
|
||||
PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_A19, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_A20, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A22, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_A23, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_B2, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_B3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B4, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2),
|
||||
PAD_CFG_GPO(GPP_B7, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B8, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B9, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B10, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_B15, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B16, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B17, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_B18, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_B19, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B20, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B22, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_B23, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_C2, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_C5, 1, PLTRST),
|
||||
PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_C8, NONE),
|
||||
PAD_NC(GPP_C9, NONE),
|
||||
PAD_NC(GPP_C10, NONE),
|
||||
PAD_NC(GPP_C11, NONE),
|
||||
PAD_NC(GPP_C12, NONE),
|
||||
PAD_NC(GPP_C13, NONE),
|
||||
PAD_NC(GPP_C14, NONE),
|
||||
PAD_NC(GPP_C15, NONE),
|
||||
PAD_NC(GPP_C16, NONE),
|
||||
PAD_NC(GPP_C17, NONE),
|
||||
PAD_NC(GPP_C18, NONE),
|
||||
PAD_NC(GPP_C19, NONE),
|
||||
PAD_NC(GPP_C20, NONE),
|
||||
PAD_NC(GPP_C21, NONE),
|
||||
PAD_NC(GPP_C22, NONE),
|
||||
PAD_NC(GPP_C23, NONE),
|
||||
PAD_CFG_GPO(GPP_D0, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_D1, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_D2, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D3, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D4, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_D6, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_D8, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D9, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_D10, NATIVE, DEEP),
|
||||
PAD_CFG_GPO(GPP_D11, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_D12, NATIVE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D13, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_D14, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_D15, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D16, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D17, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D18, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D19, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_E0, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000),
|
||||
PAD_CFG_GPO(GPP_E2, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E3, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_E4, 0, PLTRST),
|
||||
PAD_NC(GPP_E5, NONE),
|
||||
PAD_CFG_GPI(GPP_E6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E8, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E11, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_E12, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_E13, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_E15, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E16, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_E17, NONE, DEEP),
|
||||
PAD_NC(GPP_E18, NATIVE),
|
||||
PAD_NC(GPP_E19, NATIVE),
|
||||
PAD_CFG_GPO(GPP_E20, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_E21, NATIVE, DEEP),
|
||||
PAD_CFG_GPO(GPP_E22, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E23, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_F7, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_F8, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F9, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F10, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_F11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F12, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_F13, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_F14, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F15, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_F16, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_F17, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F18, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_F20, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_F21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F22, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F23, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H0, 1, PLTRST),
|
||||
PAD_CFG_GPI(GPP_H1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H3, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
|
||||
PAD_CFG_GPO(GPP_H12, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H13, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H14, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_H16, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_H19, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_H20, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_H21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H22, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_R5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R7, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_S0, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S1, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S2, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S3, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S4, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S5, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S6, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S7, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_T2, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_T3, 0, DEEP),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -1,39 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC256 */
|
||||
0x10ec0256, /* Vendor ID */
|
||||
0x15584041, /* Subsystem ID */
|
||||
11, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x15584041),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
|
||||
AZALIA_PIN_CFG(0, 0x13, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x41700001),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x21, 0x02211020),
|
||||
/* Intel, Alderlake-PHDMI */
|
||||
0x8086281c, /* Vendor ID */
|
||||
0x80860101, /* Subsystem ID */
|
||||
10, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(2, 0x80860101),
|
||||
AZALIA_PIN_CFG(2, 0x04, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x06, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x08, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0a, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0b, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0c, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0d, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0e, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0f, 0x18560010),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
@ -1,211 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#ifndef __ACPI__
|
||||
|
||||
/* Pad configuration in ramstage. */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),
|
||||
PAD_CFG_GPI(GPD2, NATIVE, PWROK),
|
||||
PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPI(GPD7, NONE, PWROK),
|
||||
PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD11, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_A6, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A7, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A8, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_A11, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_A12, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_A13, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_A14, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_A15, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
|
||||
_PAD_CFG_STRUCT(GPP_A17, 0x80100100, 0x0000),
|
||||
PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_A19, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_A20, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A22, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_A23, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_B2, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_B3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B4, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2),
|
||||
PAD_CFG_GPO(GPP_B7, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B8, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B9, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B10, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_B15, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B16, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B17, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_B18, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_B19, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B20, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B22, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_B23, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_C2, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_C5, 1, PLTRST),
|
||||
PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_C8, NONE),
|
||||
PAD_NC(GPP_C9, NONE),
|
||||
PAD_NC(GPP_C10, NONE),
|
||||
PAD_NC(GPP_C11, NONE),
|
||||
PAD_NC(GPP_C12, NONE),
|
||||
PAD_NC(GPP_C13, NONE),
|
||||
PAD_NC(GPP_C14, NONE),
|
||||
PAD_NC(GPP_C15, NONE),
|
||||
PAD_NC(GPP_C16, NONE),
|
||||
PAD_NC(GPP_C17, NONE),
|
||||
PAD_NC(GPP_C18, NONE),
|
||||
PAD_NC(GPP_C19, NONE),
|
||||
PAD_NC(GPP_C20, NONE),
|
||||
PAD_NC(GPP_C21, NONE),
|
||||
PAD_NC(GPP_C22, NONE),
|
||||
PAD_NC(GPP_C23, NONE),
|
||||
PAD_CFG_GPO(GPP_D0, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_D1, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_D2, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D3, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D4, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_D6, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_D8, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D9, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_D10, NATIVE, DEEP),
|
||||
PAD_CFG_GPO(GPP_D11, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_D12, NATIVE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D13, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_D14, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_D15, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D16, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D17, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D18, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D19, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_E0, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000),
|
||||
PAD_CFG_GPO(GPP_E2, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E3, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_E4, 0, PLTRST),
|
||||
PAD_NC(GPP_E5, NONE),
|
||||
PAD_CFG_GPI(GPP_E6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E8, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E11, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_E12, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_E13, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_E15, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E16, 0, DEEP),
|
||||
PAD_NC(GPP_E17, NONE),
|
||||
PAD_NC(GPP_E18, NATIVE),
|
||||
PAD_NC(GPP_E19, NATIVE),
|
||||
PAD_CFG_GPO(GPP_E20, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_E21, NATIVE, DEEP),
|
||||
PAD_CFG_GPO(GPP_E22, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E23, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_F7, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_F8, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F9, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F10, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_F11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F12, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_F13, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_F14, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F15, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_F16, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_F17, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F18, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_F20, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_F21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F22, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F23, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H0, 1, PLTRST),
|
||||
PAD_CFG_GPI(GPP_H1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H3, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
|
||||
PAD_CFG_GPO(GPP_H12, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H13, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H14, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_H16, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_H19, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_H20, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_H21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H22, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_R5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R7, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_S0, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S1, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S2, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S3, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S4, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S5, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S6, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S7, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_T2, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_T3, 0, DEEP),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -1,39 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC256 */
|
||||
0x10ec0256, /* Vendor ID */
|
||||
0x15584041, /* Subsystem ID */
|
||||
11, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x15584041),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
|
||||
AZALIA_PIN_CFG(0, 0x13, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x41700001),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x21, 0x02211020),
|
||||
/* Intel, Raptorlake-PHDMI */
|
||||
0x8086281f, /* Vendor ID */
|
||||
0x80860101, /* Subsystem ID */
|
||||
10, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(2, 0x80860101),
|
||||
AZALIA_PIN_CFG(2, 0x04, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x06, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x08, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0a, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0b, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0c, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0d, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0e, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0f, 0x18560010),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
@ -1,258 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2019 System76
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#ifndef __ACPI__
|
||||
|
||||
/* Pad configuration in ramstage. */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD2, NATIVE, PWROK),
|
||||
PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
|
||||
_PAD_CFG_STRUCT(GPD6, 0x44000601, 0x0000),
|
||||
_PAD_CFG_STRUCT(GPD7, 0x04000300, 0x0000),
|
||||
PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD9, NONE, PWROK),
|
||||
PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
|
||||
PAD_CFG_TERM_GPO(GPD11, 0, NONE, PWROK),
|
||||
PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_A11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A12, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_A13, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_A14, 0, DN_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A15, NONE, DEEP),
|
||||
PAD_NC(GPP_A16, NONE),
|
||||
PAD_NC(GPP_A17, NONE),
|
||||
PAD_CFG_TERM_GPO(GPP_A18, 1, NONE, DEEP),
|
||||
PAD_NC(GPP_A19, NONE),
|
||||
PAD_NC(GPP_A20, NONE),
|
||||
PAD_NC(GPP_A21, NONE),
|
||||
PAD_CFG_TERM_GPO(GPP_A22, 0, NONE, DEEP),
|
||||
PAD_NC(GPP_A23, NONE),
|
||||
PAD_CFG_GPI(GPP_B0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_B1, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B3, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_B4, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B5, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_B6, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_B7, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_B8, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_B9, NONE, PLTRST),
|
||||
PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_B11, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_B15, NONE),
|
||||
PAD_CFG_GPI(GPP_B16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B17, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_B19, NONE),
|
||||
PAD_NC(GPP_B20, NONE),
|
||||
PAD_NC(GPP_B21, NONE),
|
||||
PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_C2, NONE, DEEP),
|
||||
PAD_NC(GPP_C3, NONE),
|
||||
PAD_NC(GPP_C4, NONE),
|
||||
PAD_CFG_GPI(GPP_C5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C7, NONE, DEEP),
|
||||
PAD_NC(GPP_C8, NONE),
|
||||
PAD_CFG_TERM_GPO(GPP_C9, 1, NONE, DEEP),
|
||||
PAD_NC(GPP_C10, NONE),
|
||||
PAD_NC(GPP_C11, NONE),
|
||||
PAD_NC(GPP_C12, NONE),
|
||||
PAD_NC(GPP_C13, NONE),
|
||||
PAD_NC(GPP_C14, NONE),
|
||||
PAD_NC(GPP_C15, NONE),
|
||||
PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1),
|
||||
PAD_NC(GPP_C18, NONE),
|
||||
PAD_NC(GPP_C19, NONE),
|
||||
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_D0, NONE),
|
||||
PAD_NC(GPP_D1, NONE),
|
||||
PAD_NC(GPP_D2, NONE),
|
||||
PAD_NC(GPP_D3, NONE),
|
||||
PAD_NC(GPP_D4, NONE),
|
||||
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3),
|
||||
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3),
|
||||
PAD_NC(GPP_D7, NONE),
|
||||
PAD_NC(GPP_D8, NONE),
|
||||
PAD_NC(GPP_D9, NONE),
|
||||
PAD_NC(GPP_D10, NONE),
|
||||
PAD_NC(GPP_D11, NONE),
|
||||
PAD_NC(GPP_D12, NONE),
|
||||
PAD_NC(GPP_D13, NONE),
|
||||
PAD_NC(GPP_D14, NONE),
|
||||
PAD_NC(GPP_D15, NONE),
|
||||
PAD_NC(GPP_D16, NONE),
|
||||
PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_D21, NONE),
|
||||
PAD_NC(GPP_D22, NONE),
|
||||
PAD_NC(GPP_D23, NONE),
|
||||
PAD_CFG_GPI(GPP_E0, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E2, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_E3, 0x44000101, 0x0000),
|
||||
PAD_CFG_GPI(GPP_E4, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_E5, UP_20K, DEEP),
|
||||
PAD_NC(GPP_E6, NONE),
|
||||
_PAD_CFG_STRUCT(GPP_E7, 0x40800100, 0x3000),
|
||||
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_E9, NONE),
|
||||
PAD_NC(GPP_E10, NONE),
|
||||
PAD_NC(GPP_E11, NONE),
|
||||
PAD_NC(GPP_E12, NONE),
|
||||
PAD_NC(GPP_F0, NONE),
|
||||
PAD_NC(GPP_F1, NONE),
|
||||
PAD_NC(GPP_F2, NONE),
|
||||
PAD_NC(GPP_F3, NONE),
|
||||
PAD_NC(GPP_F4, NONE),
|
||||
PAD_CFG_GPI(GPP_F5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F6, NONE, DEEP),
|
||||
PAD_NC(GPP_F7, NONE),
|
||||
PAD_NC(GPP_F8, NONE),
|
||||
PAD_NC(GPP_F9, NONE),
|
||||
PAD_NC(GPP_F10, NONE),
|
||||
PAD_NC(GPP_F11, NONE),
|
||||
PAD_NC(GPP_F12, NONE),
|
||||
PAD_NC(GPP_F13, NONE),
|
||||
PAD_CFG_GPI(GPP_F14, UP_20K, DEEP),
|
||||
PAD_NC(GPP_F15, NONE),
|
||||
PAD_NC(GPP_F16, NONE),
|
||||
PAD_NC(GPP_F17, NONE),
|
||||
PAD_NC(GPP_F18, NONE),
|
||||
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_F22, 1, NONE, PLTRST),
|
||||
PAD_CFG_TERM_GPO(GPP_F23, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G3, UP_20K, DEEP),
|
||||
PAD_NC(GPP_G4, NONE),
|
||||
PAD_NC(GPP_G5, NONE),
|
||||
PAD_NC(GPP_G6, NONE),
|
||||
PAD_NC(GPP_G7, NONE),
|
||||
PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1),
|
||||
_PAD_CFG_STRUCT(GPP_H1, 0x84000300, 0x0000),
|
||||
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),
|
||||
_PAD_CFG_STRUCT(GPP_H3, 0x84000300, 0x0000),
|
||||
_PAD_CFG_STRUCT(GPP_H4, 0x84000300, 0x0000),
|
||||
_PAD_CFG_STRUCT(GPP_H5, 0x84000300, 0x0000),
|
||||
_PAD_CFG_STRUCT(GPP_H6, 0x84000300, 0x0000),
|
||||
_PAD_CFG_STRUCT(GPP_H7, 0x84000300, 0x0000),
|
||||
_PAD_CFG_STRUCT(GPP_H8, 0x84000300, 0x0000),
|
||||
_PAD_CFG_STRUCT(GPP_H9, 0x84000300, 0x0000),
|
||||
PAD_CFG_GPI(GPP_H10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H14, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H15, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H17, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H18, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H21, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H22, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H23, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I0, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1),
|
||||
_PAD_CFG_STRUCT(GPP_I3, 0x46880100, 0x0000),
|
||||
PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_I5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I6, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_I9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I14, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_J1, 1, NONE, DEEP),
|
||||
PAD_NC(GPP_J2, NONE),
|
||||
PAD_NC(GPP_J3, NONE),
|
||||
PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_J10, NONE),
|
||||
PAD_NC(GPP_J11, NONE),
|
||||
PAD_NC(GPP_K0, NONE),
|
||||
PAD_NC(GPP_K1, NONE),
|
||||
PAD_NC(GPP_K2, NONE),
|
||||
_PAD_CFG_STRUCT(GPP_K3, 0x80880100, 0x3000),
|
||||
PAD_NC(GPP_K4, NONE),
|
||||
PAD_NC(GPP_K5, NONE),
|
||||
_PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x3000),
|
||||
PAD_NC(GPP_K7, NONE),
|
||||
PAD_CFG_GPI(GPP_K8, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K11, NONE, DEEP),
|
||||
PAD_NC(GPP_K12, NONE),
|
||||
PAD_NC(GPP_K13, NONE),
|
||||
PAD_NC(GPP_K14, NONE),
|
||||
PAD_NC(GPP_K15, NONE),
|
||||
PAD_NC(GPP_K16, NONE),
|
||||
PAD_NC(GPP_K17, NONE),
|
||||
PAD_NC(GPP_K18, NONE),
|
||||
_PAD_CFG_STRUCT(GPP_K19, 0x42000100, 0x3000),
|
||||
_PAD_CFG_STRUCT(GPP_K20, 0x44000101, 0x0000),
|
||||
PAD_CFG_GPI(GPP_K21, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_K22, 0x80000100, 0x0000),
|
||||
PAD_CFG_NF(GPP_K23, NONE, DEEP, NF1),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -1,258 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2019 System76
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#ifndef __ACPI__
|
||||
|
||||
/* Pad configuration in ramstage. */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD1, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD2, DN_20K, PWROK),
|
||||
PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD4, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD5, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD6, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD7, NONE, PWROK),
|
||||
PAD_CFG_NF(GPD8, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD9, DN_20K, PWROK),
|
||||
_PAD_CFG_STRUCT(GPD10, 0x04000601, 0x1000),
|
||||
PAD_CFG_TERM_GPO(GPD11, 0, DN_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_A0, 1, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
|
||||
_PAD_CFG_STRUCT(GPP_A7, 0x80100100, 0x0000),
|
||||
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_A11, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A12, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_A13, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A14, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1),
|
||||
_PAD_CFG_STRUCT(GPP_A16, 0x44000101, 0x1000),
|
||||
_PAD_CFG_STRUCT(GPP_A17, 0x44000101, 0x0000),
|
||||
PAD_CFG_TERM_GPO(GPP_A18, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A20, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_A21, 0x44000101, 0x0000),
|
||||
PAD_CFG_TERM_GPO(GPP_A22, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A23, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_B1, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_B2, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_B3, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_B4, 0, UP_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_B5, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_B6, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_B7, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_B8, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_B9, 0, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_B11, 0, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_B12, 0x44000601, 0x0000),
|
||||
_PAD_CFG_STRUCT(GPP_B13, 0x44000601, 0x1000),
|
||||
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_B15, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_B16, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_B17, 0, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_B19, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_B20, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_B21, 0, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_B23, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_C2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C4, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_C5, 0, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_C8, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C9, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_C10, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_C11, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_C12, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_C13, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_C14, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_C15, 0, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_C18, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_C19, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_D0, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_D1, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_D2, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_D3, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_D4, 0, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3),
|
||||
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3),
|
||||
PAD_CFG_TERM_GPO(GPP_D7, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_D8, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_D9, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_D10, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_D11, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_D12, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_D13, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_D14, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_D15, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_D16, 0, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_D21, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_D22, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_D23, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E0, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E2, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_E3, 0, UP_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_E4, 1, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_E5, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_E6, 0, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_E7, 0x80800100, 0x0000),
|
||||
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
|
||||
_PAD_CFG_STRUCT(GPP_E9, 0x44000101, 0x3000),
|
||||
_PAD_CFG_STRUCT(GPP_E10, 0x44000501, 0x3000),
|
||||
_PAD_CFG_STRUCT(GPP_E11, 0x44000501, 0x3000),
|
||||
_PAD_CFG_STRUCT(GPP_E12, 0x44000501, 0x3000),
|
||||
PAD_CFG_TERM_GPO(GPP_F0, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_F1, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_F2, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_F3, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_F4, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F5, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_F6, 0x44000101, 0x0000),
|
||||
PAD_CFG_TERM_GPO(GPP_F7, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_F8, 1, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_F9, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F14, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_F15, 0x44000501, 0x3000),
|
||||
_PAD_CFG_STRUCT(GPP_F16, 0x44000501, 0x3000),
|
||||
_PAD_CFG_STRUCT(GPP_F17, 0x44000501, 0x3000),
|
||||
_PAD_CFG_STRUCT(GPP_F18, 0x44000501, 0x3000),
|
||||
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_F22, 0, NONE, PLTRST),
|
||||
PAD_CFG_TERM_GPO(GPP_F23, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G0, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_G1, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_G2, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_G3, 0x44000101, 0x0000),
|
||||
PAD_CFG_GPI(GPP_G4, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_G5, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_G6, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_G7, 0, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_H1, 0, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_H3, 0, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_H5, DN_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_H6, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_H7, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_H8, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_H9, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_H10, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_H11, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_H12, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H13, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_H14, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H15, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_H16, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_H17, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_H18, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_H19, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_H20, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_H21, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_H22, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H23, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1),
|
||||
_PAD_CFG_STRUCT(GPP_I1, 0x46880100, 0x0000),
|
||||
PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1),
|
||||
_PAD_CFG_STRUCT(GPP_I3, 0x46880100, 0x0000),
|
||||
PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_I7, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_I8, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_I9, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_I10, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I11, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_I12, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_I13, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_I14, 0, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_J1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_J2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_J3, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_J10, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_J11, DN_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K0, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K1, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K2, 0, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_K3, 0x40880100, 0x0000),
|
||||
PAD_CFG_TERM_GPO(GPP_K4, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K5, 0, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000),
|
||||
PAD_CFG_TERM_GPO(GPP_K7, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K8, 1, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K9, 1, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K10, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K11, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K12, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K13, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K14, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K15, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K16, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K17, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K18, 0, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_K19, 0x42800101, 0x0000),
|
||||
PAD_CFG_TERM_GPO(GPP_K20, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K21, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_K22, 0x44000101, 0x0000),
|
||||
PAD_CFG_TERM_GPO(GPP_K23, 1, NONE, DEEP),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -1,258 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2019 System76
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#ifndef __ACPI__
|
||||
|
||||
/* Pad configuration in ramstage. */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
PAD_CFG_GPI(GPD0, NONE, PWROK),
|
||||
PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD2, NATIVE, PWROK),
|
||||
PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD7, NONE, PWROK),
|
||||
PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD9, NONE, PWROK),
|
||||
PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD11, NONE, PWROK),
|
||||
PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
|
||||
_PAD_CFG_STRUCT(GPP_A7, 0x80100100, 0x0000),
|
||||
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_A11, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A12, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_A16, DN_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A17, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_A18, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A21, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_A22, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A23, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B4, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_B5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B8, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B9, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_B11, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_B15, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B17, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B18, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B21, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B22, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B23, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_C2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C8, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C14, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C15, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_C20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C21, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C22, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C23, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D4, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3),
|
||||
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3),
|
||||
PAD_CFG_GPI(GPP_D7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D8, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D14, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D15, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D17, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D18, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_D21, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D22, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D23, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E0, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E6, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_E7, 0x80800100, 0x0000),
|
||||
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F8, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F14, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F15, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F17, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F18, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_F22, 1, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_F23, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G0, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_G1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G7, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_H1, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_H3, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_H6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H8, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H14, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H15, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H17, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H18, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H21, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H22, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H23, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1),
|
||||
_PAD_CFG_STRUCT(GPP_I1, 0x46880100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_I2, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_I3, 0x46880100, 0x0000),
|
||||
PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_I7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I8, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I14, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J1, NONE, DEEP, NF2),
|
||||
PAD_CFG_GPI(GPP_J2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_J3, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_J10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_J11, DN_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K2, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_K3, 0x80880100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_K4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K5, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_K7, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K8, 1, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K9, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K13, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K14, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K15, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K17, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K18, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K19, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K20, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K21, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_K22, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K23, NONE, DEEP),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -1,43 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC293 */
|
||||
0x10ec0293, /* Vendor ID */
|
||||
0x15588520, /* Subsystem ID */
|
||||
12, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x15588520),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
|
||||
AZALIA_PIN_CFG(0, 0x13, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x15, 0x02211020),
|
||||
AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x02a11040),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x41738205),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
|
||||
/* Intel, KabylakeHDMI */
|
||||
0x8086280b, /* Vendor ID */
|
||||
0x80860101, /* Subsystem ID */
|
||||
4, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(2, 0x80860101),
|
||||
AZALIA_PIN_CFG(2, 0x05, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x06, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x07, 0x18560010),
|
||||
/* Nvidia, GPU99HDMI/DP */
|
||||
0x10de0099, /* Vendor ID */
|
||||
0x10de0000, /* Subsystem ID */
|
||||
5, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x10de0000),
|
||||
AZALIA_PIN_CFG(0, 0x04, 0x185600f0),
|
||||
AZALIA_PIN_CFG(0, 0x05, 0x185600f0),
|
||||
AZALIA_PIN_CFG(0, 0x06, 0x585600f0),
|
||||
AZALIA_PIN_CFG(0, 0x07, 0x585600f0),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
@ -1,259 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#ifndef __ACPI__
|
||||
|
||||
/* Pad configuration in ramstage. */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),
|
||||
PAD_CFG_GPI(GPD2, NATIVE, PWROK),
|
||||
PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPI(GPD7, NONE, PWROK),
|
||||
PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPO(GPD9, 0, PWROK),
|
||||
PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPI(GPD11, NONE, PWROK),
|
||||
_PAD_CFG_STRUCT(GPD12, 0x04000300, 0x0000),
|
||||
PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_A7, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A8, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A9, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A10, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A11, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A12, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A13, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A14, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_B0, 0x40100100, 0x3000),
|
||||
PAD_CFG_GPI(GPP_B1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B2, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_B3, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_B4, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_B6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B8, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_B11, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_B15, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_B16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B17, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B18, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B21, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B22, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B23, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_C2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C8, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C14, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C15, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_C18, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C21, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_C22, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_C23, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D3, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3),
|
||||
PAD_CFG_GPI(GPP_D7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D8, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_D9, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_D11, NATIVE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D14, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_D16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D17, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D18, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D21, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D22, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D23, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E0, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E4, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E5, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPI(GPP_E6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E7, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E12, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF2),
|
||||
PAD_CFG_GPI(GPP_F1, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_F2, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_F3, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_F4, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_F5, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_F6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F7, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_F8, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_F9, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_F10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F11, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_F12, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_F13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F14, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F15, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F16, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_F17, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_F18, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_F22, NONE),
|
||||
PAD_CFG_GPI(GPP_F23, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G2, DN_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_G3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G8, NATIVE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G10, NATIVE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G11, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_G12, 0x44001300, 0x3c00),
|
||||
_PAD_CFG_STRUCT(GPP_G13, 0x44001300, 0x3c00),
|
||||
PAD_CFG_GPI(GPP_G14, NATIVE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G15, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H0, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_H4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H8, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H14, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H15, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_H16, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_H17, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_H18, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H21, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H22, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_H23, 1, DEEP),
|
||||
PAD_CFG_NF(GPP_I0, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPI(GPP_I1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I4, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_I7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I8, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_I9, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_I10, DN_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_I11, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_I12, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_I13, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_I14, NONE, PLTRST),
|
||||
PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J1, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_J8, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_J9, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_K0, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_K1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K5, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_K6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_K7, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_K8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_K9, NONE, DEEP, NF1),
|
||||
_PAD_CFG_STRUCT(GPP_K10, 0x46880100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_K11, DN_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_R5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R8, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R11, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_R12, 0x40100100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_R13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R14, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R15, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R17, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R18, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_S0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_S1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_S2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_S3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_S4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_S5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_S6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_S7, NONE, DEEP),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -1,45 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC256 */
|
||||
0x10ec0256, /* Vendor ID */
|
||||
0x15585017, /* Subsystem ID */
|
||||
11, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x15585017),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
|
||||
AZALIA_PIN_CFG(0, 0x13, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x02a11040),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x41700001),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x21, 0x02211020),
|
||||
/* Intel, TigerlakeHDMI */
|
||||
0x80862812, /* Vendor ID */
|
||||
0x80860101, /* Subsystem ID */
|
||||
10, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(2, 0x80860101),
|
||||
AZALIA_PIN_CFG(2, 0x04, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x06, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x08, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0a, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0b, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0c, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0d, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0e, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0f, 0x18560010),
|
||||
/* Nvidia, GPUa0HDMI/DP */
|
||||
0x10de00a0, /* Vendor ID */
|
||||
0x10de0000, /* Subsystem ID */
|
||||
2, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x10de0000),
|
||||
AZALIA_PIN_CFG(0, 0x04, 0x185600f0),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
@ -1,259 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#ifndef __ACPI__
|
||||
|
||||
/* Pad configuration in ramstage. */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),
|
||||
_PAD_CFG_STRUCT(GPD2, 0x00080500, 0x0000),
|
||||
PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPI(GPD7, NONE, PWROK),
|
||||
PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPO(GPD9, 0, PWROK),
|
||||
PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD11, NONE, PWROK, NF1),
|
||||
_PAD_CFG_STRUCT(GPD12, 0x04000300, 0x0000),
|
||||
PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_A7, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A8, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A9, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A10, UP_20K, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_A11, 0x80100100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_A12, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A13, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A14, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_B0, 0x40100100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_B1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B2, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_B3, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_B4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B6, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_B9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B11, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_B15, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_B16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B17, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B18, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B21, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B22, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B23, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_C2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C8, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C14, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C15, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_C18, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C21, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_C22, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_C23, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D3, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3),
|
||||
PAD_CFG_GPI(GPP_D7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D8, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_D9, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_D11, NATIVE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D14, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_D16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D17, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D18, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D21, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D22, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_D23, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_E0, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E3, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E4, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E7, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E12, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF2),
|
||||
PAD_CFG_GPI(GPP_F1, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_F2, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_F3, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_F4, 1, DEEP),
|
||||
PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_F6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F7, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_F8, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_F9, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_F10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F14, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F15, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F16, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_F17, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_F18, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_F22, NONE),
|
||||
PAD_CFG_GPO(GPP_F23, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_G0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G2, DN_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_G3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G8, NATIVE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G10, NATIVE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G11, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_G12, 0x44001300, 0x3c00),
|
||||
_PAD_CFG_STRUCT(GPP_G13, 0x44001300, 0x3c00),
|
||||
PAD_CFG_GPI(GPP_G14, NATIVE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G15, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H0, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_H5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H8, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H14, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H15, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_H16, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_H17, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_H18, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H21, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_H22, NONE, PLTRST),
|
||||
PAD_CFG_GPO(GPP_H23, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_I0, NONE, PLTRST),
|
||||
_PAD_CFG_STRUCT(GPP_I1, 0x46880100, 0x0000),
|
||||
_PAD_CFG_STRUCT(GPP_I2, 0x46880100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_I3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I4, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_I7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I8, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_I9, 1, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_I10, 0, DN_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_I11, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_I12, NONE, DEEP, NF2),
|
||||
PAD_CFG_GPI(GPP_I13, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_I14, NONE, PLTRST),
|
||||
PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J1, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_J8, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_J9, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_K0, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_K1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K5, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_K6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_K7, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_K8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_K9, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_K10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K11, NONE, PLTRST),
|
||||
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R5, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_R6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R8, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R11, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_R12, 0x40100100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_R13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R14, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R15, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R17, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R18, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_S0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_S1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_S2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_S3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_S4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_S5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_S6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_S7, NONE, DEEP),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -1,46 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC256 */
|
||||
0x10ec0256, /* Vendor ID */
|
||||
0x155850e1, /* Subsystem ID */
|
||||
11, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x155850e1),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
|
||||
AZALIA_PIN_CFG(0, 0x13, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x02a11040),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x41789c6d),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x21, 0x02211020),
|
||||
/* Intel, TigerlakeHDMI */
|
||||
0x80862812, /* Vendor ID */
|
||||
0x80860101, /* Subsystem ID */
|
||||
10, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(2, 0x80860101),
|
||||
AZALIA_PIN_CFG(2, 0x04, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x06, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x08, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0a, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0b, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0c, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0d, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0e, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0f, 0x18560010),
|
||||
/* Nvidia, GPU9fHDMI/DP */
|
||||
0x10de009f, /* Vendor ID */
|
||||
0x10de0000, /* Subsystem ID */
|
||||
3, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x10de0000),
|
||||
AZALIA_PIN_CFG(0, 0x04, 0x185600f0),
|
||||
AZALIA_PIN_CFG(0, 0x05, 0x185600f0),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
@ -1,259 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#ifndef __ACPI__
|
||||
|
||||
/* Pad configuration in ramstage. */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),
|
||||
PAD_CFG_GPI(GPD2, NATIVE, PWROK),
|
||||
PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPI(GPD7, NONE, PWROK),
|
||||
PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPO(GPD9, 0, PWROK),
|
||||
PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPI(GPD11, NONE, PWROK),
|
||||
_PAD_CFG_STRUCT(GPD12, 0x04000300, 0x0000),
|
||||
PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_A7, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A8, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A9, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A10, UP_20K, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_A11, 0x80100100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_A12, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A13, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A14, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_B0, 0x40100100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_B1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B2, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_B3, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_B4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B6, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_B9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B11, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_B15, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_B16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B17, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B18, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B21, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B22, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B23, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_C2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C8, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C14, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C15, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_C18, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C21, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_C22, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_C23, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D3, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3),
|
||||
PAD_CFG_GPI(GPP_D7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D8, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_D9, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_D11, NATIVE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D14, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_D16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D17, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D18, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D21, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D22, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_D23, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_E0, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E3, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E4, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E7, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E12, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF2),
|
||||
PAD_CFG_GPI(GPP_F1, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_F2, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_F3, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_F4, 1, DEEP),
|
||||
PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_F6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F7, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_F8, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_F9, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_F10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F14, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F15, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F16, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_F17, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_F18, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_F22, NONE),
|
||||
PAD_CFG_GPO(GPP_F23, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_G0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G2, DN_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_G3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G8, NATIVE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G10, NATIVE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G11, NONE, DEEP),
|
||||
PAD_NC(GPP_G12, NATIVE),
|
||||
PAD_NC(GPP_G13, NATIVE),
|
||||
PAD_CFG_GPI(GPP_G14, NATIVE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G15, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H0, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_H5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H8, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H14, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H15, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_H16, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_H17, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_H18, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H21, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_H22, NONE, PLTRST),
|
||||
PAD_CFG_GPO(GPP_H23, 1, DEEP),
|
||||
PAD_CFG_NF(GPP_I0, NONE, PWROK, NF1),
|
||||
_PAD_CFG_STRUCT(GPP_I1, 0x46880100, 0x0000),
|
||||
_PAD_CFG_STRUCT(GPP_I2, 0x46880100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_I3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I4, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_I7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I8, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_I9, 1, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_I10, 0, DN_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_I11, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_I12, NONE, DEEP, NF2),
|
||||
PAD_CFG_GPI(GPP_I13, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_I14, NONE, PLTRST),
|
||||
PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J1, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_J8, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_J9, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_K0, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_K1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K5, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_K6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_K7, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_K8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_K9, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_K10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K11, NONE, PLTRST),
|
||||
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R5, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_R6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R8, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R11, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_R12, 0x40100100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_R13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R14, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R15, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R17, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R18, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_S0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_S1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_S2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_S3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_S4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_S5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_S6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_S7, NONE, DEEP),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -1,46 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC256 */
|
||||
0x10ec0256, /* Vendor ID */
|
||||
0x155850e2, /* Subsystem ID */
|
||||
11, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x155850e2),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
|
||||
AZALIA_PIN_CFG(0, 0x13, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x02a11040),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x41789c6d),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x21, 0x02211020),
|
||||
/* Intel, TigerlakeHDMI */
|
||||
0x80862812, /* Vendor ID */
|
||||
0x80860101, /* Subsystem ID */
|
||||
10, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(2, 0x80860101),
|
||||
AZALIA_PIN_CFG(2, 0x04, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x06, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x08, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0a, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0b, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0c, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0d, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0e, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0f, 0x18560010),
|
||||
/* Nvidia, GPU9fHDMI/DP */
|
||||
0x10de009f, /* Vendor ID */
|
||||
0x10de0000, /* Subsystem ID */
|
||||
3, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x10de0000),
|
||||
AZALIA_PIN_CFG(0, 0x04, 0x185600f0),
|
||||
AZALIA_PIN_CFG(0, 0x05, 0x185600f0),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
@ -1,211 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#ifndef __ACPI__
|
||||
|
||||
/* Pad configuration in ramstage. */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPO(GPD7, 0, DEEP),
|
||||
PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPO(GPD9, 0, PWROK),
|
||||
PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD11, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_A6, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A7, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A8, 1, PLTRST),
|
||||
PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_A11, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A12, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A13, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_A14, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_A15, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
|
||||
_PAD_CFG_STRUCT(GPP_A17, 0x80100100, 0x0000),
|
||||
PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_A19, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_A20, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A22, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A23, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_B2, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_B3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B4, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_B5, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B6, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B7, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B8, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B9, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B10, 0, DEEP),
|
||||
PAD_NC(GPP_B11, NONE),
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
_PAD_CFG_STRUCT(GPP_B14, 0x44001100, 0x0000),
|
||||
PAD_CFG_GPO(GPP_B15, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B16, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B17, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B18, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B19, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B20, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B22, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B23, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_C2, 1, PLTRST),
|
||||
PAD_CFG_GPI(GPP_C3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C4, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_C5, 0, DEEP),
|
||||
PAD_NC(GPP_C6, NONE),
|
||||
PAD_NC(GPP_C7, NONE),
|
||||
PAD_NC(GPP_C8, NONE),
|
||||
PAD_NC(GPP_C9, NONE),
|
||||
PAD_NC(GPP_C10, NONE),
|
||||
PAD_NC(GPP_C11, NONE),
|
||||
PAD_NC(GPP_C12, NONE),
|
||||
PAD_NC(GPP_C13, NONE),
|
||||
PAD_NC(GPP_C14, NONE),
|
||||
PAD_NC(GPP_C15, NONE),
|
||||
PAD_NC(GPP_C16, NONE),
|
||||
PAD_NC(GPP_C17, NONE),
|
||||
PAD_NC(GPP_C18, NONE),
|
||||
PAD_NC(GPP_C19, NONE),
|
||||
PAD_NC(GPP_C20, NONE),
|
||||
PAD_NC(GPP_C21, NONE),
|
||||
PAD_NC(GPP_C22, NONE),
|
||||
PAD_NC(GPP_C23, NONE),
|
||||
PAD_CFG_GPO(GPP_D0, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_D1, NONE, DEEP),
|
||||
PAD_NC(GPP_D2, NONE),
|
||||
PAD_CFG_GPO(GPP_D3, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_D4, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_D9, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D10, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF2),
|
||||
PAD_CFG_GPI(GPP_D13, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_D14, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_D15, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D16, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_D17, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D18, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D19, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_E0, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000),
|
||||
PAD_CFG_GPI(GPP_E2, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_E3, 1, PLTRST),
|
||||
PAD_CFG_GPI(GPP_E4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E5, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_E6, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_E7, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_E8, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_E10, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_E11, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_E12, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E13, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_E15, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E16, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_E17, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_E18, 0, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_E19, 0x44001600, 0x3c00),
|
||||
PAD_CFG_GPO(GPP_E20, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E21, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_F7, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_F8, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F9, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F10, 0, DEEP),
|
||||
PAD_NC(GPP_F11, NONE),
|
||||
PAD_CFG_GPI(GPP_F12, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_F13, NONE, PLTRST),
|
||||
PAD_NC(GPP_F14, NONE),
|
||||
PAD_NC(GPP_F15, NONE),
|
||||
PAD_CFG_GPO(GPP_F16, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F17, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F18, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_F20, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_F21, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_H0, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H1, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H2, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_H3, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_H6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H7, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_H8, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H9, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_H10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H11, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_H12, 0, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_H13, 0x04001500, 0x0000),
|
||||
PAD_CFG_GPO(GPP_H14, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_H16, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_H19, 0, DEEP),
|
||||
PAD_NC(GPP_H20, NONE),
|
||||
PAD_NC(GPP_H21, NONE),
|
||||
PAD_NC(GPP_H22, NONE),
|
||||
PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_R5, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_R6, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_R7, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S0, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S1, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S2, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S3, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S4, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S5, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S6, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S7, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_T2, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_T3, 0, DEEP),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -1,39 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC256 */
|
||||
0x10ec0256, /* Vendor ID */
|
||||
0x1558866d, /* Subsystem ID */
|
||||
11, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x1558866d),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
|
||||
AZALIA_PIN_CFG(0, 0x13, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x02a11040),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x41700001),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x21, 0x02211020),
|
||||
/* Intel, Alderlake-PHDMI */
|
||||
0x8086281c, /* Vendor ID */
|
||||
0x80860101, /* Subsystem ID */
|
||||
10, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(2, 0x80860101),
|
||||
AZALIA_PIN_CFG(2, 0x04, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x06, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x08, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0a, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0b, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0c, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0d, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0e, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0f, 0x18560010),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
@ -1,211 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#ifndef __ACPI__
|
||||
|
||||
/* Pad configuration in ramstage. */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPO(GPD7, 0, DEEP),
|
||||
PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPO(GPD9, 0, PWROK),
|
||||
PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD11, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_A6, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A7, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A8, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_A11, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_A13, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_A14, 1, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_A15, 0x46880100, 0x0000),
|
||||
PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
|
||||
_PAD_CFG_STRUCT(GPP_A17, 0x80100100, 0x0000),
|
||||
_PAD_CFG_STRUCT(GPP_A18, 0x46880100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_A19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A20, NONE, PLTRST),
|
||||
PAD_CFG_GPO(GPP_A21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A22, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A23, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_B2, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_B3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B4, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_B5, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B6, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B7, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B8, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B9, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B10, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
_PAD_CFG_STRUCT(GPP_B14, 0x44001100, 0x0000),
|
||||
PAD_CFG_GPO(GPP_B15, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B16, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B17, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B18, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B19, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B20, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B22, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B23, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_C2, 1, PLTRST),
|
||||
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_C5, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_C8, NONE),
|
||||
PAD_NC(GPP_C9, NONE),
|
||||
PAD_NC(GPP_C10, NONE),
|
||||
PAD_NC(GPP_C11, NONE),
|
||||
PAD_NC(GPP_C12, NONE),
|
||||
PAD_NC(GPP_C13, NONE),
|
||||
PAD_NC(GPP_C14, NONE),
|
||||
PAD_NC(GPP_C15, NONE),
|
||||
PAD_NC(GPP_C16, NONE),
|
||||
PAD_NC(GPP_C17, NONE),
|
||||
PAD_NC(GPP_C18, NONE),
|
||||
PAD_NC(GPP_C19, NONE),
|
||||
PAD_NC(GPP_C20, NONE),
|
||||
PAD_NC(GPP_C21, NONE),
|
||||
PAD_NC(GPP_C22, NONE),
|
||||
PAD_NC(GPP_C23, NONE),
|
||||
PAD_CFG_GPO(GPP_D0, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_D1, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_D2, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D3, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_D4, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_D9, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D10, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D11, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_D12, NATIVE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D13, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_D14, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_D15, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D16, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D17, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D18, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D19, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_E0, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000),
|
||||
PAD_CFG_GPI(GPP_E2, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_E3, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_E4, 0, PLTRST),
|
||||
PAD_CFG_GPO(GPP_E5, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E6, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_E7, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_E8, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_E10, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_E11, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_E12, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_E13, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_E15, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E16, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_E17, NONE, DEEP),
|
||||
PAD_NC(GPP_E18, NATIVE),
|
||||
PAD_NC(GPP_E19, NATIVE),
|
||||
PAD_CFG_GPO(GPP_E20, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E22, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E23, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_F7, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_F8, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F9, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F10, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F11, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_F12, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_F13, NONE, PLTRST),
|
||||
PAD_CFG_GPO(GPP_F14, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F15, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_F16, NONE, PLTRST),
|
||||
PAD_CFG_GPO(GPP_F17, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F18, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_F20, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_F21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F22, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F23, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H0, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H1, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H2, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_H3, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_H8, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H9, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_H10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H11, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_H12, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_H13, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_H14, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H15, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H16, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H17, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_H19, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_H20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H21, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_H22, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_R5, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_R6, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_R7, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S0, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S1, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S2, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S3, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S4, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S5, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S6, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S7, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_T2, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_T3, 0, DEEP),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -1,46 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC256 */
|
||||
0x10ec0256, /* Vendor ID */
|
||||
0x1558867c, /* Subsystem ID */
|
||||
11, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x1558867c),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
|
||||
AZALIA_PIN_CFG(0, 0x13, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x02a11040),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x41700001),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x21, 0x02211020),
|
||||
/* Intel, Alderlake-PHDMI */
|
||||
0x8086281c, /* Vendor ID */
|
||||
0x80860101, /* Subsystem ID */
|
||||
10, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(2, 0x80860101),
|
||||
AZALIA_PIN_CFG(2, 0x04, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x06, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x08, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0a, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0b, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0c, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0d, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0e, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0f, 0x18560010),
|
||||
/* Nvidia, GPU9fHDMI/DP */
|
||||
0x10de009f, /* Vendor ID */
|
||||
0x10de0000, /* Subsystem ID */
|
||||
3, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x10de0000),
|
||||
AZALIA_PIN_CFG(0, 0x04, 0x185600f0),
|
||||
AZALIA_PIN_CFG(0, 0x06, 0x185600f0),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
@ -1,211 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#ifndef __ACPI__
|
||||
|
||||
/* Pad configuration in ramstage. */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPO(GPD7, 0, DEEP),
|
||||
PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPO(GPD9, 0, PWROK),
|
||||
PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD11, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_A6, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A7, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A8, 1, PLTRST),
|
||||
PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_A11, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A12, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A13, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_A14, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_A15, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
|
||||
_PAD_CFG_STRUCT(GPP_A17, 0x80100100, 0x0000),
|
||||
PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_A19, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_A20, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A22, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A23, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_B2, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_B3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B4, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_B5, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B6, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B7, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B8, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B9, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B10, 0, DEEP),
|
||||
PAD_NC(GPP_B11, NONE),
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
_PAD_CFG_STRUCT(GPP_B14, 0x44001100, 0x0000),
|
||||
PAD_CFG_GPO(GPP_B15, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B16, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B17, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B18, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B19, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B20, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B22, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B23, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_C2, 1, PLTRST),
|
||||
PAD_CFG_GPI(GPP_C3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C4, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_C5, 0, DEEP),
|
||||
PAD_NC(GPP_C6, NONE),
|
||||
PAD_NC(GPP_C7, NONE),
|
||||
PAD_NC(GPP_C8, NONE),
|
||||
PAD_NC(GPP_C9, NONE),
|
||||
PAD_NC(GPP_C10, NONE),
|
||||
PAD_NC(GPP_C11, NONE),
|
||||
PAD_NC(GPP_C12, NONE),
|
||||
PAD_NC(GPP_C13, NONE),
|
||||
PAD_NC(GPP_C14, NONE),
|
||||
PAD_NC(GPP_C15, NONE),
|
||||
PAD_NC(GPP_C16, NONE),
|
||||
PAD_NC(GPP_C17, NONE),
|
||||
PAD_NC(GPP_C18, NONE),
|
||||
PAD_NC(GPP_C19, NONE),
|
||||
PAD_NC(GPP_C20, NONE),
|
||||
PAD_NC(GPP_C21, NONE),
|
||||
PAD_NC(GPP_C22, NONE),
|
||||
PAD_NC(GPP_C23, NONE),
|
||||
PAD_CFG_GPO(GPP_D0, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_D1, NONE, DEEP),
|
||||
PAD_NC(GPP_D2, NONE),
|
||||
PAD_CFG_GPO(GPP_D3, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_D4, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_D9, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D10, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF2),
|
||||
PAD_CFG_GPI(GPP_D13, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_D14, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_D15, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D16, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_D17, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D18, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D19, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_E0, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000),
|
||||
PAD_CFG_GPI(GPP_E2, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_E3, 1, PLTRST),
|
||||
PAD_CFG_GPI(GPP_E4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E5, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_E6, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_E7, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_E8, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_E10, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_E11, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_E12, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E13, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_E15, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E16, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_E17, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_E18, 0, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_E19, 0x44001600, 0x3c00),
|
||||
PAD_CFG_GPO(GPP_E20, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E21, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_F7, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_F8, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F9, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F10, 0, DEEP),
|
||||
PAD_NC(GPP_F11, NONE),
|
||||
PAD_CFG_GPI(GPP_F12, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_F13, NONE, PLTRST),
|
||||
PAD_NC(GPP_F14, NONE),
|
||||
PAD_NC(GPP_F15, NONE),
|
||||
PAD_CFG_GPO(GPP_F16, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F17, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F18, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_F20, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_F21, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_H0, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H1, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H2, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_H3, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_H6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H7, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_H8, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H9, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_H10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H11, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_H12, 0, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_H13, 0x04001500, 0x0000),
|
||||
PAD_CFG_GPO(GPP_H14, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_H16, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_H19, 0, DEEP),
|
||||
PAD_NC(GPP_H20, NONE),
|
||||
PAD_NC(GPP_H21, NONE),
|
||||
PAD_NC(GPP_H22, NONE),
|
||||
PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_R5, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_R6, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_R7, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S0, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S1, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S2, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S3, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S4, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S5, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S6, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S7, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_T2, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_T3, 0, DEEP),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -1,39 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC256 */
|
||||
0x10ec0256, /* Vendor ID */
|
||||
0x15585630, /* Subsystem ID */
|
||||
11, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x15585630),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
|
||||
AZALIA_PIN_CFG(0, 0x13, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x02a11040),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x41700001),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x21, 0x02211020),
|
||||
/* Intel, Raptorlake-PHDMI */
|
||||
0x8086281f, /* Vendor ID */
|
||||
0x80860101, /* Subsystem ID */
|
||||
10, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(2, 0x80860101),
|
||||
AZALIA_PIN_CFG(2, 0x04, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x06, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x08, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0a, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0b, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0c, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0d, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0e, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0f, 0x18560010),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
@ -1,213 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#ifndef __ACPI__
|
||||
|
||||
/* Pad configuration in ramstage. */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),
|
||||
PAD_CFG_GPI(GPD2, NONE, PWROK),
|
||||
PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPD7, 1, NONE, PWROK),
|
||||
PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
|
||||
PAD_CFG_TERM_GPO(GPD9, 0, NONE, PWROK),
|
||||
PAD_CFG_NF(GPD10, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD11, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_A7, NONE),
|
||||
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_A9, NONE, DEEP, NF3),
|
||||
PAD_NC(GPP_A10, NONE),
|
||||
PAD_NC(GPP_A11, NONE),
|
||||
PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_A13, 1, NONE, PLTRST),
|
||||
PAD_NC(GPP_A14, NONE),
|
||||
PAD_NC(GPP_A15, NONE),
|
||||
PAD_NC(GPP_A16, NONE),
|
||||
PAD_NC(GPP_A17, NONE),
|
||||
PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_A19, NONE),
|
||||
PAD_NC(GPP_A20, NONE),
|
||||
PAD_NC(GPP_A21, NONE),
|
||||
PAD_NC(GPP_A22, NONE),
|
||||
PAD_CFG_TERM_GPO(GPP_A23, 0, NONE, PLTRST),
|
||||
PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_B2, UP_20K, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_B3, 0x80800100, 0x0000),
|
||||
PAD_NC(GPP_B4, NONE),
|
||||
PAD_NC(GPP_B5, NONE),
|
||||
PAD_NC(GPP_B6, NONE),
|
||||
PAD_NC(GPP_B7, NONE),
|
||||
PAD_NC(GPP_B8, NONE),
|
||||
PAD_NC(GPP_B9, NONE),
|
||||
PAD_NC(GPP_B10, NONE),
|
||||
PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_B14, 0, NONE, DEEP),
|
||||
PAD_NC(GPP_B15, NONE),
|
||||
PAD_NC(GPP_B16, NONE),
|
||||
PAD_NC(GPP_B17, NONE),
|
||||
PAD_NC(GPP_B18, NONE),
|
||||
PAD_NC(GPP_B19, NONE),
|
||||
PAD_NC(GPP_B20, NONE),
|
||||
PAD_NC(GPP_B21, NONE),
|
||||
PAD_NC(GPP_B22, NONE),
|
||||
PAD_CFG_TERM_GPO(GPP_B23, 0, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_C2, 1, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_C5, NONE),
|
||||
PAD_CFG_NF(GPP_C6, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPP_C7, NONE, PWROK, NF1),
|
||||
PAD_NC(GPP_C8, NONE),
|
||||
_PAD_CFG_STRUCT(GPP_C9, 0x40100100, 0x3000),
|
||||
PAD_NC(GPP_C10, NONE),
|
||||
PAD_NC(GPP_C11, NONE),
|
||||
PAD_NC(GPP_C12, NONE),
|
||||
PAD_CFG_TERM_GPO(GPP_C13, 1, NONE, PLTRST),
|
||||
PAD_NC(GPP_C14, DN_20K),
|
||||
PAD_NC(GPP_C15, NONE),
|
||||
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_C20, NONE),
|
||||
PAD_NC(GPP_C21, NONE),
|
||||
PAD_CFG_TERM_GPO(GPP_C22, 1, NONE, PLTRST),
|
||||
_PAD_CFG_STRUCT(GPP_C23, 0x40880100, 0x0000),
|
||||
PAD_CFG_TERM_GPO(GPP_D0, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D2, DN_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D3, DN_20K, DEEP),
|
||||
PAD_NC(GPP_D4, NONE),
|
||||
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
|
||||
_PAD_CFG_STRUCT(GPP_D9, 0x84000301, 0x0000),
|
||||
PAD_NC(GPP_D10, NONE),
|
||||
PAD_CFG_GPI(GPP_D11, DN_20K, DEEP),
|
||||
PAD_NC(GPP_D12, NONE),
|
||||
PAD_NC(GPP_D13, NONE),
|
||||
PAD_CFG_TERM_GPO(GPP_D14, 1, NONE, PLTRST),
|
||||
PAD_NC(GPP_D15, NONE),
|
||||
PAD_NC(GPP_D16, NONE),
|
||||
PAD_CFG_GPI(GPP_D17, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D18, NONE, DEEP),
|
||||
PAD_NC(GPP_D19, NONE),
|
||||
PAD_NC(GPP_E0, NONE),
|
||||
PAD_CFG_TERM_GPO(GPP_E1, 0, NONE, PLTRST),
|
||||
PAD_NC(GPP_E2, NONE),
|
||||
PAD_CFG_GPI(GPP_E3, DN_20K, DEEP),
|
||||
PAD_NC(GPP_E4, NONE),
|
||||
PAD_NC(GPP_E5, NONE),
|
||||
PAD_NC(GPP_E6, NONE),
|
||||
PAD_NC(GPP_E7, NONE),
|
||||
PAD_NC(GPP_E8, NONE),
|
||||
PAD_NC(GPP_E9, NONE),
|
||||
PAD_NC(GPP_E10, NONE),
|
||||
PAD_NC(GPP_E11, NONE),
|
||||
PAD_NC(GPP_E12, NONE),
|
||||
PAD_NC(GPP_E13, NONE),
|
||||
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E15, DN_20K, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_E16, 0x82840100, 0x0000),
|
||||
PAD_NC(GPP_E17, NONE),
|
||||
PAD_NC(GPP_E18, NATIVE),
|
||||
PAD_NC(GPP_E19, NATIVE),
|
||||
_PAD_CFG_STRUCT(GPP_E20, 0x40880100, 0x0000),
|
||||
PAD_NC(GPP_E21, NONE),
|
||||
PAD_NC(GPP_E22, NONE),
|
||||
PAD_NC(GPP_E23, NONE),
|
||||
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
|
||||
PAD_NC(GPP_F4, NONE),
|
||||
PAD_NC(GPP_F5, NONE),
|
||||
PAD_NC(GPP_F6, NONE),
|
||||
PAD_NC(GPP_F7, NONE),
|
||||
PAD_NC(GPP_F8, NONE),
|
||||
PAD_NC(GPP_F9, NONE),
|
||||
PAD_NC(GPP_F10, NONE),
|
||||
PAD_NC(GPP_F11, NONE),
|
||||
PAD_NC(GPP_F12, NONE),
|
||||
PAD_NC(GPP_F13, NONE),
|
||||
PAD_NC(GPP_F14, NONE),
|
||||
PAD_NC(GPP_F15, NONE),
|
||||
PAD_NC(GPP_F16, NONE),
|
||||
PAD_CFG_GPI(GPP_F17, NONE, PLTRST),
|
||||
PAD_NC(GPP_F18, NONE),
|
||||
PAD_NC(GPP_F19, NONE),
|
||||
PAD_NC(GPP_F20, NONE),
|
||||
PAD_CFG_GPI(GPP_F21, DN_20K, DEEP),
|
||||
PAD_NC(GPP_F22, NONE),
|
||||
PAD_NC(GPP_F23, NONE),
|
||||
PAD_NC(GPP_H0, DN_20K),
|
||||
PAD_NC(GPP_H1, DN_20K),
|
||||
PAD_NC(GPP_H2, DN_20K),
|
||||
PAD_CFG_GPI(GPP_H3, DN_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_H6, NONE, DEEP),
|
||||
PAD_NC(GPP_H7, NONE),
|
||||
PAD_CFG_GPI(GPP_H8, DN_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H9, DN_20K, DEEP),
|
||||
PAD_NC(GPP_H10, NONE),
|
||||
PAD_NC(GPP_H11, NONE),
|
||||
PAD_NC(GPP_H12, NONE),
|
||||
PAD_NC(GPP_H13, NONE),
|
||||
PAD_NC(GPP_H14, NONE),
|
||||
PAD_NC(GPP_H15, NONE),
|
||||
PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_H19, NONE),
|
||||
PAD_NC(GPP_H20, NONE),
|
||||
PAD_NC(GPP_H21, NONE),
|
||||
PAD_NC(GPP_H22, NONE),
|
||||
PAD_NC(GPP_H23, NONE),
|
||||
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_R5, NONE),
|
||||
PAD_NC(GPP_R6, NONE),
|
||||
PAD_NC(GPP_R7, NONE),
|
||||
PAD_NC(GPP_S0, NONE),
|
||||
PAD_NC(GPP_S1, NONE),
|
||||
PAD_NC(GPP_S2, NONE),
|
||||
PAD_NC(GPP_S3, NONE),
|
||||
PAD_NC(GPP_S4, NONE),
|
||||
PAD_NC(GPP_S5, NONE),
|
||||
PAD_CFG_GPI(GPP_S6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_S7, NONE, DEEP),
|
||||
PAD_NC(GPP_T2, NONE),
|
||||
PAD_NC(GPP_T3, NONE),
|
||||
PAD_NC(GPP_U4, NONE),
|
||||
PAD_NC(GPP_U5, NONE),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -1,40 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC293 */
|
||||
0x10ec0293, /* Vendor ID */
|
||||
0x155814a1, /* Subsystem ID */
|
||||
12, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x155814a1),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
|
||||
AZALIA_PIN_CFG(0, 0x13, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x15, 0x02211020),
|
||||
AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x41748245),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
|
||||
/* Intel, TigerlakeHDMI */
|
||||
0x80862812, /* Vendor ID */
|
||||
0x80860101, /* Subsystem ID */
|
||||
10, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(2, 0x80860101),
|
||||
AZALIA_PIN_CFG(2, 0x04, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x06, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x08, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0a, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0b, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0c, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0d, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0e, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0f, 0x18560010),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
@ -1,211 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#ifndef __ACPI__
|
||||
|
||||
/* Pad configuration in ramstage. */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),
|
||||
PAD_CFG_GPO(GPD2, 0, DEEP),
|
||||
PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPI(GPD7, NONE, PWROK),
|
||||
PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPO(GPD9, 0, PWROK),
|
||||
PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD11, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_A6, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A7, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A8, 1, PLTRST),
|
||||
PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_A11, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_A13, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_A14, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A15, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_A17, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_A19, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A20, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A21, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_A22, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_A23, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_B3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B4, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_B5, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B6, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B7, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B8, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B9, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B10, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_B15, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B16, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B17, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_B18, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B19, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B20, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B22, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B23, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_C2, 1, PLTRST),
|
||||
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_C5, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_C8, NONE),
|
||||
PAD_NC(GPP_C9, NONE),
|
||||
PAD_NC(GPP_C10, NONE),
|
||||
PAD_NC(GPP_C11, NONE),
|
||||
PAD_NC(GPP_C12, NONE),
|
||||
PAD_NC(GPP_C13, NONE),
|
||||
PAD_NC(GPP_C14, NONE),
|
||||
PAD_NC(GPP_C15, NONE),
|
||||
PAD_NC(GPP_C16, NONE),
|
||||
PAD_NC(GPP_C17, NONE),
|
||||
PAD_NC(GPP_C18, NONE),
|
||||
PAD_NC(GPP_C19, NONE),
|
||||
PAD_NC(GPP_C20, NONE),
|
||||
PAD_NC(GPP_C21, NONE),
|
||||
PAD_NC(GPP_C22, NONE),
|
||||
PAD_NC(GPP_C23, NONE),
|
||||
PAD_CFG_GPO(GPP_D0, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_D1, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_D2, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D3, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D4, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_D8, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D9, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D10, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D11, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_D12, NATIVE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D13, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_D14, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_D15, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D16, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_D17, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D18, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D19, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_E0, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000),
|
||||
PAD_CFG_GPO(GPP_E2, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E3, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_E4, 0, PLTRST),
|
||||
PAD_NC(GPP_E5, NONE),
|
||||
PAD_CFG_GPO(GPP_E6, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_E7, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_E8, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_E10, 0, DEEP),
|
||||
PAD_NC(GPP_E11, NONE),
|
||||
_PAD_CFG_STRUCT(GPP_E12, 0x40100100, 0x0000),
|
||||
PAD_CFG_GPO(GPP_E13, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_E15, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E16, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E17, 0, DEEP),
|
||||
PAD_NC(GPP_E18, NATIVE),
|
||||
PAD_NC(GPP_E19, NATIVE),
|
||||
PAD_CFG_GPO(GPP_E20, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E22, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E23, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_F7, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_F8, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F9, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F10, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_F11, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F12, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_F13, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_F14, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F15, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F16, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_F17, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_F18, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_F20, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_F21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F22, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F23, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H0, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_H1, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H2, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_H3, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_H8, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H9, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_H10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H11, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_H12, 0x44001500, 0x0000),
|
||||
PAD_CFG_GPO(GPP_H13, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H14, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_H16, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_H19, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H20, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H22, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H23, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_R5, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_R6, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_R7, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S0, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S1, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S2, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S3, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S4, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S5, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S6, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S7, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_T2, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_T3, 0, DEEP),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -1,39 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC256 */
|
||||
0x10ec0256, /* Vendor ID */
|
||||
0x15587718, /* Subsystem ID */
|
||||
11, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x15587718),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
|
||||
AZALIA_PIN_CFG(0, 0x13, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x41700001),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x21, 0x02211020),
|
||||
/* Intel, Alderlake-PHDMI */
|
||||
0x8086281c, /* Vendor ID */
|
||||
0x80860101, /* Subsystem ID */
|
||||
10, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(2, 0x80860101),
|
||||
AZALIA_PIN_CFG(2, 0x04, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x06, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x08, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0a, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0b, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0c, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0d, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0e, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0f, 0x18560010),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
@ -1,211 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#ifndef __ACPI__
|
||||
|
||||
/* Pad configuration in ramstage. */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),
|
||||
PAD_CFG_GPO(GPD2, 0, DEEP),
|
||||
PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPI(GPD7, NONE, PWROK),
|
||||
PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPO(GPD9, 0, PWROK),
|
||||
PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPO(GPD11, 0, PWROK),
|
||||
PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_A6, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A7, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A8, 1, PLTRST),
|
||||
PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_A11, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_A13, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_A14, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A15, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_A17, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_A19, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A20, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A21, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_A22, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_A23, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_B3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B4, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_B5, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B6, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B7, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B8, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B9, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B10, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_B15, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B16, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B17, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_B18, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B19, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B20, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B22, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B23, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_C2, 1, PLTRST),
|
||||
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_C5, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_C8, NONE),
|
||||
PAD_NC(GPP_C9, NONE),
|
||||
PAD_NC(GPP_C10, NONE),
|
||||
PAD_NC(GPP_C11, NONE),
|
||||
PAD_NC(GPP_C12, NONE),
|
||||
PAD_NC(GPP_C13, NONE),
|
||||
PAD_NC(GPP_C14, NONE),
|
||||
PAD_NC(GPP_C15, NONE),
|
||||
PAD_NC(GPP_C16, NONE),
|
||||
PAD_NC(GPP_C17, NONE),
|
||||
PAD_NC(GPP_C18, NONE),
|
||||
PAD_NC(GPP_C19, NONE),
|
||||
PAD_NC(GPP_C20, NONE),
|
||||
PAD_NC(GPP_C21, NONE),
|
||||
PAD_NC(GPP_C22, NONE),
|
||||
PAD_NC(GPP_C23, NONE),
|
||||
PAD_CFG_GPO(GPP_D0, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_D1, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_D2, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D3, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D4, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_D8, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D9, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D10, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D11, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_D12, NATIVE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D13, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_D14, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_D15, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D16, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_D17, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D18, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D19, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_E0, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000),
|
||||
PAD_CFG_GPO(GPP_E2, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E3, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_E4, 0, PLTRST),
|
||||
PAD_NC(GPP_E5, NONE),
|
||||
PAD_CFG_GPO(GPP_E6, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_E7, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_E8, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_E10, 0, DEEP),
|
||||
PAD_NC(GPP_E11, NONE),
|
||||
_PAD_CFG_STRUCT(GPP_E12, 0x40800100, 0x0000),
|
||||
PAD_CFG_GPO(GPP_E13, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_E15, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E16, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E17, 0, DEEP),
|
||||
PAD_NC(GPP_E18, NATIVE),
|
||||
PAD_NC(GPP_E19, NATIVE),
|
||||
PAD_CFG_GPO(GPP_E20, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E22, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E23, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_F7, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_F8, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F9, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F10, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_F11, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F12, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_F13, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_F14, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F15, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F16, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_F17, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_F18, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_F20, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_F21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F22, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F23, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H0, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_H1, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H2, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_H3, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_H8, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H9, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_H10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H11, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_H12, 0x44001500, 0x0000),
|
||||
PAD_CFG_GPO(GPP_H13, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H14, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_H16, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_H19, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H20, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H22, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H23, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_R5, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_R6, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_R7, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S0, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S1, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S2, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S3, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S4, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S5, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S6, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S7, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_T2, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_T3, 0, DEEP),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -1,39 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC256 */
|
||||
0x10ec0256, /* Vendor ID */
|
||||
0x15587724, /* Subsystem ID */
|
||||
11, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x15587724),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
|
||||
AZALIA_PIN_CFG(0, 0x13, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x41700001),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x21, 0x02211020),
|
||||
/* Intel, Raptorlake-PHDMI */
|
||||
0x8086281f, /* Vendor ID */
|
||||
0x80860101, /* Subsystem ID */
|
||||
10, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(2, 0x80860101),
|
||||
AZALIA_PIN_CFG(2, 0x04, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x06, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x08, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0a, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0b, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0c, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0d, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0e, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0f, 0x18560010),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
@ -1,218 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2019 System76
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#ifndef __ACPI__
|
||||
|
||||
/* Pad configuration in ramstage. */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
PAD_CFG_GPI(GPD0, NONE, PWROK),
|
||||
PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD2, NATIVE, PWROK),
|
||||
PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD7, NONE, PWROK),
|
||||
PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD9, NONE, PWROK),
|
||||
PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD11, NONE, PWROK),
|
||||
PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_A7, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_A8, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1),
|
||||
_PAD_CFG_STRUCT(GPP_A11, 0x80100100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_A12, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_A16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A17, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A18, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A19, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_A20, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A21, NONE, DEEP),
|
||||
PAD_NC(GPP_A22, NONE),
|
||||
PAD_CFG_GPI(GPP_A23, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B2, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_B3, 0x80100100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_B4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B6, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_B11, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_B15, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B17, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B18, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B21, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B22, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B23, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_C2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C8, NONE, DEEP),
|
||||
PAD_NC(GPP_C9, NONE),
|
||||
PAD_CFG_TERM_GPO(GPP_C10, 0, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_C11, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_C12, 1, NONE, PLTRST),
|
||||
PAD_CFG_TERM_GPO(GPP_C13, 1, NONE, PLTRST),
|
||||
PAD_CFG_TERM_GPO(GPP_C14, 0, NONE, PLTRST),
|
||||
PAD_NC(GPP_C15, NONE),
|
||||
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_C18, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C21, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C22, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C23, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D7, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_D8, 1, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_D9, 0x40880100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_D10, NONE, DEEP),
|
||||
PAD_NC(GPP_D11, NONE),
|
||||
PAD_CFG_GPI(GPP_D12, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_D13, 1, NONE, PLTRST),
|
||||
PAD_CFG_TERM_GPO(GPP_D14, 1, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_D15, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_D16, 1, NONE, PWROK),
|
||||
PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_D21, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D22, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D23, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E0, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E2, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E4, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E7, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E12, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E15, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_E16, 0x80880100, 0x0000),
|
||||
PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E22, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E23, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_F1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F3, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F7, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_F10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F14, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F15, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F17, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F18, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F21, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F22, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F23, DN_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_G0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H0, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3),
|
||||
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3),
|
||||
PAD_CFG_GPI(GPP_H3, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_H6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H8, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H14, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H15, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H17, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_H19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H21, NONE, DEEP),
|
||||
PAD_NC(GPP_H22, NONE),
|
||||
PAD_CFG_GPI(GPP_H23, NONE, DEEP),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -1,34 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC293 */
|
||||
0x10ec0293, /* Vendor ID */
|
||||
0x15581401, /* Subsystem ID */
|
||||
12, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x15581401),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
|
||||
AZALIA_PIN_CFG(0, 0x13, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x15, 0x02211020),
|
||||
AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x41748245),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
|
||||
/* Intel, KabylakeHDMI */
|
||||
0x8086280b, /* Vendor ID */
|
||||
0x80860101, /* Subsystem ID */
|
||||
4, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(2, 0x80860101),
|
||||
AZALIA_PIN_CFG(2, 0x05, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x06, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x07, 0x18560010),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
@ -1,211 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#ifndef __ACPI__
|
||||
|
||||
/* Pad configuration in ramstage. */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),
|
||||
PAD_CFG_GPO(GPD2, 0, DEEP),
|
||||
PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPO(GPD7, 0, DEEP),
|
||||
PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPO(GPD9, 0, PWROK),
|
||||
PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD11, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1),
|
||||
_PAD_CFG_STRUCT(GPP_A6, 0x80100100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_A7, NONE, PLTRST),
|
||||
PAD_CFG_GPO(GPP_A8, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_A11, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_A13, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_A14, 0, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_A15, 0x46880100, 0x0000),
|
||||
PAD_CFG_GPO(GPP_A16, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_A17, 0, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_A18, 0x46880100, 0x0000),
|
||||
PAD_CFG_GPO(GPP_A19, 0, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_A20, 0x46880100, 0x0000),
|
||||
PAD_CFG_GPO(GPP_A21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A22, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_A23, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_B2, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_B3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B4, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
|
||||
PAD_CFG_GPO(GPP_B9, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B10, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_B15, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B16, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B17, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B18, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B19, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B20, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B22, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B23, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_C2, 1, PLTRST),
|
||||
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_C5, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_C8, NONE),
|
||||
PAD_NC(GPP_C9, NONE),
|
||||
PAD_NC(GPP_C10, NONE),
|
||||
PAD_NC(GPP_C11, NONE),
|
||||
PAD_NC(GPP_C12, NONE),
|
||||
PAD_NC(GPP_C13, NONE),
|
||||
PAD_NC(GPP_C14, NONE),
|
||||
PAD_NC(GPP_C15, NONE),
|
||||
PAD_NC(GPP_C16, NONE),
|
||||
PAD_NC(GPP_C17, NONE),
|
||||
PAD_NC(GPP_C18, NONE),
|
||||
PAD_NC(GPP_C19, NONE),
|
||||
PAD_NC(GPP_C20, NONE),
|
||||
PAD_NC(GPP_C21, NONE),
|
||||
PAD_NC(GPP_C22, NONE),
|
||||
PAD_NC(GPP_C23, NONE),
|
||||
PAD_CFG_GPO(GPP_D0, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_D1, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_D2, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D3, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D4, 1, PLTRST),
|
||||
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_D6, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_D9, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D10, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D11, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_D12, NATIVE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D13, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_D14, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_D15, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D16, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D17, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D18, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D19, 1, PLTRST),
|
||||
PAD_CFG_GPI(GPP_E0, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000),
|
||||
PAD_CFG_GPI(GPP_E2, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_E3, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_E4, 0, PLTRST),
|
||||
PAD_CFG_GPO(GPP_E5, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_E6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E8, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_E9, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_E10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E11, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_E12, 0x80100100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_E13, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_E15, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E16, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_E17, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_E18, 0x44001300, 0x3c00),
|
||||
_PAD_CFG_STRUCT(GPP_E19, 0x44001300, 0x3c00),
|
||||
PAD_CFG_GPO(GPP_E20, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E22, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E23, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_F7, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F8, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F9, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F10, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F11, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F12, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F13, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F14, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_F15, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F17, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_F18, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_F20, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_F21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F22, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F23, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H0, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H1, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_H2, 1, PLTRST),
|
||||
PAD_CFG_GPI(GPP_H3, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_H8, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H9, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_H10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H11, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_H12, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H13, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H14, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H15, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H16, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H17, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_H20, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H22, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_R5, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_R6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R7, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_S0, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S1, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S2, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S3, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S4, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S5, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S6, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S7, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_T2, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_T3, 0, DEEP),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -1,48 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC1220 */
|
||||
0x10ec1220, /* Vendor ID */
|
||||
0x155865f5, /* Subsystem ID */
|
||||
12, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x155865f5),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x0421101f),
|
||||
AZALIA_PIN_CFG(0, 0x15, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x04a11040),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x04451150),
|
||||
/* Intel, Alderlake-PHDMI */
|
||||
0x8086281c, /* Vendor ID */
|
||||
0x80860101, /* Subsystem ID */
|
||||
10, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(2, 0x80860101),
|
||||
AZALIA_PIN_CFG(2, 0x04, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x06, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x08, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0a, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0b, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0c, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0d, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0e, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0f, 0x18560010),
|
||||
/* Nvidia, GPU9dHDMI/DP */
|
||||
0x10de009d, /* Vendor ID */
|
||||
0x10de0000, /* Subsystem ID */
|
||||
4, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x10de0000),
|
||||
AZALIA_PIN_CFG(0, 0x04, 0x185600f0),
|
||||
AZALIA_PIN_CFG(0, 0x06, 0x185600f0),
|
||||
AZALIA_PIN_CFG(0, 0x07, 0x185600f0),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
@ -1,211 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#ifndef __ACPI__
|
||||
|
||||
/* Pad configuration in ramstage. */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPO(GPD7, 0, DEEP),
|
||||
PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPO(GPD9, 0, PWROK),
|
||||
PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPO(GPD11, 1, DEEP),
|
||||
PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_A6, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_A7, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_A8, 1, DEEP),
|
||||
PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_A11, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_A12, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_A13, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_A14, 1, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_A15, 0x86880100, 0x0000),
|
||||
PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
|
||||
_PAD_CFG_STRUCT(GPP_A17, 0x80100100, 0x0000),
|
||||
_PAD_CFG_STRUCT(GPP_A18, 0x86880100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_A19, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_A20, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_A21, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_A22, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_A23, 1, DEEP),
|
||||
PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_B2, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_B3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B4, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_B5, 0x44000a01, 0x0000),
|
||||
_PAD_CFG_STRUCT(GPP_B6, 0x44000a01, 0x0000),
|
||||
PAD_CFG_GPO(GPP_B7, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_B8, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_B9, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_B10, 1, DEEP),
|
||||
PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_B15, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_B16, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_B17, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_B18, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B19, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_B20, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_B21, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_B22, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_B23, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_C2, 1, PLTRST),
|
||||
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_C5, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_C8, NONE),
|
||||
PAD_NC(GPP_C9, NONE),
|
||||
PAD_NC(GPP_C10, NONE),
|
||||
PAD_NC(GPP_C11, NONE),
|
||||
PAD_NC(GPP_C12, NONE),
|
||||
PAD_NC(GPP_C13, NONE),
|
||||
PAD_NC(GPP_C14, NONE),
|
||||
PAD_NC(GPP_C15, NONE),
|
||||
PAD_NC(GPP_C16, NONE),
|
||||
PAD_NC(GPP_C17, NONE),
|
||||
PAD_NC(GPP_C18, NONE),
|
||||
PAD_NC(GPP_C19, NONE),
|
||||
PAD_NC(GPP_C20, NONE),
|
||||
PAD_NC(GPP_C21, NONE),
|
||||
PAD_NC(GPP_C22, NONE),
|
||||
PAD_NC(GPP_C23, NONE),
|
||||
PAD_CFG_GPO(GPP_D0, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_D1, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_D2, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D3, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_D4, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_D6, 1, DEEP),
|
||||
PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_D9, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_D10, 0, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_D11, 0x44001700, 0x3c00),
|
||||
PAD_CFG_GPO(GPP_D12, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_D13, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_D14, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_D15, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_D16, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_D17, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_D18, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_D19, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_E0, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000),
|
||||
PAD_CFG_GPI(GPP_E2, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_E3, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_E4, 0, PLTRST),
|
||||
PAD_CFG_GPO(GPP_E5, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E6, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_E7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E8, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_E10, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_E11, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_E12, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_E13, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_E15, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_E16, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_E17, NONE, DEEP),
|
||||
PAD_NC(GPP_E18, NATIVE),
|
||||
PAD_NC(GPP_E19, NATIVE),
|
||||
PAD_CFG_GPO(GPP_E20, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_E21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E22, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_E23, 1, DEEP),
|
||||
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_F7, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_F8, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_F9, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_F10, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F11, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_F12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F13, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_F14, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_F15, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_F16, NONE, PLTRST),
|
||||
PAD_CFG_GPO(GPP_F17, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_F18, 1, DEEP),
|
||||
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_F20, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_F21, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_F22, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_F23, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_H0, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H1, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_H2, 1, PLTRST),
|
||||
PAD_CFG_GPI(GPP_H3, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2),
|
||||
PAD_CFG_GPO(GPP_H9, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_H10, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_H11, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H12, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_H13, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_H14, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_H15, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_H16, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_H17, 1, DEEP),
|
||||
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_H20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H21, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_H22, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_R5, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_R6, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_R7, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_S0, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_S1, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_S2, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_S3, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_S4, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_S5, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_S6, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_S7, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_T2, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_T3, 1, DEEP),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -1,49 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC1220 */
|
||||
0x10ec1220, /* Vendor ID */
|
||||
0x155866a2, /* Subsystem ID */
|
||||
12, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x155866a2),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60120),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x0421101f),
|
||||
AZALIA_PIN_CFG(0, 0x15, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x04a11030),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
|
||||
/* Intel, Raptorlake-PHDMI */
|
||||
0x8086281f, /* Vendor ID */
|
||||
0x80860101, /* Subsystem ID */
|
||||
10, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(2, 0x80860101),
|
||||
AZALIA_PIN_CFG(2, 0x04, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x06, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x08, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0a, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0b, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0c, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0d, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0e, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0f, 0x18560010),
|
||||
/* Nvidia, GenericHDMI */
|
||||
0x10de00a6, /* Vendor ID */
|
||||
0x10de0000, /* Subsystem ID */
|
||||
5, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x10de0000),
|
||||
AZALIA_PIN_CFG(0, 0x04, 0x185600f0),
|
||||
AZALIA_PIN_CFG(0, 0x05, 0x585600f0),
|
||||
AZALIA_PIN_CFG(0, 0x06, 0x185600f0),
|
||||
AZALIA_PIN_CFG(0, 0x07, 0x585600f0),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
@ -1,245 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#ifndef __ACPI__
|
||||
|
||||
/* Pad configuration in ramstage. */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD2, NATIVE, PWROK),
|
||||
PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD6, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_GPI(GPD7, UP_20K, PWROK),
|
||||
PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD9, UP_20K, PWROK),
|
||||
PAD_CFG_NF(GPD10, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_TERM_GPO(GPD11, 1, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
|
||||
_PAD_CFG_STRUCT(GPP_A11, 0x80100100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_A12, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A13, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A14, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A15, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A16, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A17, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A18, UP_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_A19, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A21, UP_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_A22, 1, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_A23, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B0, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_B1, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_B2, UP_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_B3, 1, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_B4, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B5, UP_20K, PLTRST),
|
||||
PAD_CFG_GPI(GPP_B6, UP_20K, PLTRST),
|
||||
PAD_CFG_TERM_GPO(GPP_B7, 1, NONE, PLTRST),
|
||||
PAD_CFG_TERM_GPO(GPP_B8, 1, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_B9, UP_20K, PLTRST),
|
||||
PAD_CFG_TERM_GPO(GPP_B10, 0, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_B11, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_B12, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_B15, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_B16, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_B17, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_B18, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_B19, UP_20K, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_B20, 0x42040100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_B21, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_B22, UP_20K, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_B23, 0x80880100, 0x3000),
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_C2, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_C3, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_C4, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_C5, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_C6, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_C7, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_C8, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C9, DN_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_C10, DN_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_C11, DN_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_C12, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_C13, 1, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_C14, 1, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_C15, 1, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_C18, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_C19, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_C20, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C21, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C22, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C23, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_D0, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D1, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D2, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D3, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D4, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3),
|
||||
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3),
|
||||
PAD_CFG_GPI(GPP_D7, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D8, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D9, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D10, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D11, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D12, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D13, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D14, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D15, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D16, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_D17, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D18, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D19, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D20, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_D21, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D22, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D23, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_E0, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E2, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_E3, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_E4, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_E5, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_E6, UP_20K, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_E7, 0x80100100, 0x0000),
|
||||
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E9, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_E10, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_E11, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_E12, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F0, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_F2, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F3, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F4, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F5, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_F7, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F8, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F9, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F10, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F11, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F12, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F13, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F14, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F15, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F16, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F17, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F18, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_F22, 1, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_F23, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G0, UP_20K, DEEP),
|
||||
PAD_NC(GPP_G1, NONE),
|
||||
PAD_CFG_GPI(GPP_G2, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_G3, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_G4, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_G5, UP_20K, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_G6, 0x40880100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_G7, UP_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_H0, 0, NONE, PLTRST),
|
||||
PAD_CFG_TERM_GPO(GPP_H1, 0, NONE, PLTRST),
|
||||
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_H3, 0, NONE, PLTRST),
|
||||
PAD_CFG_TERM_GPO(GPP_H4, 0, NONE, PLTRST),
|
||||
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_H10, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H11, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H12, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H13, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H14, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H15, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H16, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H17, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H18, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H19, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H20, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H21, DN_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H22, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H23, UP_20K, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_I0, 0x46880100, 0x0000),
|
||||
_PAD_CFG_STRUCT(GPP_I1, 0x46880100, 0x0000),
|
||||
_PAD_CFG_STRUCT(GPP_I2, 0x46880100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_I3, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_I5, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_I6, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_I7, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_I8, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_I9, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_I10, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_I11, UP_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_I12, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I13, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_I14, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_J1, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_J2, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_J3, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_J8, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_J9, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_J10, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_J11, UP_20K, DEEP),
|
||||
PAD_NC(GPP_K0, NONE),
|
||||
PAD_CFG_GPI(GPP_K1, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K2, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K3, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K4, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K5, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K6, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K7, UP_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K8, 1, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K9, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K10, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K11, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K12, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K13, UP_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K14, 0, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K15, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K16, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K17, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K18, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K19, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K20, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K21, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K22, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K23, UP_20K, DEEP),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -1,43 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC1220 */
|
||||
0x10ec1220, /* Vendor ID */
|
||||
0x155896e1, /* Subsystem ID */
|
||||
12, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x155896e1),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60140),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x0421101f),
|
||||
AZALIA_PIN_CFG(0, 0x15, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x04a11050),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x04451130),
|
||||
/* Intel, KabylakeHDMI */
|
||||
0x8086280b, /* Vendor ID */
|
||||
0x80860101, /* Subsystem ID */
|
||||
4, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(2, 0x80860101),
|
||||
AZALIA_PIN_CFG(2, 0x05, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x06, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x07, 0x18560010),
|
||||
/* Nvidia, GPU93HDMI/DP */
|
||||
0x10de0093, /* Vendor ID */
|
||||
0x155895e1, /* Subsystem ID */
|
||||
5, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x155895e1),
|
||||
AZALIA_PIN_CFG(0, 0x04, 0x585600f0),
|
||||
AZALIA_PIN_CFG(0, 0x05, 0x185600f0),
|
||||
AZALIA_PIN_CFG(0, 0x06, 0x185600f0),
|
||||
AZALIA_PIN_CFG(0, 0x07, 0x185600f0),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
@ -1,258 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2019 System76
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#ifndef __ACPI__
|
||||
|
||||
/* Pad configuration in ramstage. */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD2, NATIVE, PWROK),
|
||||
PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD6, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_GPI(GPD7, UP_20K, PWROK),
|
||||
PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD9, UP_20K, PWROK),
|
||||
PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD11, UP_20K, PWROK),
|
||||
PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A10, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_A11, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A12, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_A15, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A16, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A17, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A18, UP_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_A19, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A21, UP_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_A22, 1, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_A23, 1, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_B0, 0x42080100, 0x3000),
|
||||
PAD_CFG_GPI(GPP_B1, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_B2, UP_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_B3, 1, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_B4, 1, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_B6, UP_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_B7, 1, NONE, PLTRST),
|
||||
PAD_CFG_TERM_GPO(GPP_B8, 1, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_B9, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_B10, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_B11, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_B12, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_B15, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_B16, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_B17, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_B18, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_B19, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_B20, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_B21, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_B22, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_C2, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_C3, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_C4, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_C5, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_C6, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_C7, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_C8, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_C9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C10, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_C11, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_C12, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_C13, UP_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_C14, 1, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_C15, 1, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_C18, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_C19, NONE, PLTRST, NF1),
|
||||
PAD_CFG_GPI(GPP_C20, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_C21, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_C22, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_C23, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D0, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D1, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D2, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D3, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D4, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3),
|
||||
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3),
|
||||
PAD_CFG_GPI(GPP_D7, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D8, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D9, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D10, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D11, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D12, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D13, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D14, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D15, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D16, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_D17, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D18, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D19, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D20, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_D21, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D22, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D23, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_E0, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E2, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_E3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E4, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
|
||||
_PAD_CFG_STRUCT(GPP_E6, 0x82040100, 0x0000),
|
||||
_PAD_CFG_STRUCT(GPP_E7, 0x80800100, 0x0000),
|
||||
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E9, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_E10, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_E11, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_E12, UP_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_F0, 0, NONE, PLTRST),
|
||||
PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_F2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F3, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F4, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F5, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_F7, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F8, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F9, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F10, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F11, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F12, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F13, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F14, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F15, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F16, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F17, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F18, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_F22, 1, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_F23, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G0, DN_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_G1, DN_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_G2, DN_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_G3, DN_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_G4, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_G5, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_G6, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_G7, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H0, NONE, PLTRST),
|
||||
PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1),
|
||||
_PAD_CFG_STRUCT(GPP_H4, 0x40880100, 0x3000),
|
||||
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_H7, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H8, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H9, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H10, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H11, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H14, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H15, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_H16, 0, NONE, PLTRST),
|
||||
PAD_CFG_TERM_GPO(GPP_H17, 0, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_H18, UP_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_H19, 1, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_H20, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H21, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H22, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H23, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I0, UP_20K, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_I1, 0x46880100, 0x0000),
|
||||
_PAD_CFG_STRUCT(GPP_I2, 0x46880100, 0x0000),
|
||||
_PAD_CFG_STRUCT(GPP_I3, 0x46880100, 0x0000),
|
||||
PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_I5, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_I6, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_I7, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_I8, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_I9, UP_20K, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_I10, 0x82880100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_I11, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_I12, DN_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_I13, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_I14, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_J1, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_J2, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_J3, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_J8, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_J9, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_J10, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_J11, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K0, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K1, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K2, UP_20K, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_K3, 0x80880100, 0x3000),
|
||||
PAD_CFG_GPI(GPP_K4, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K5, UP_20K, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_K7, UP_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K8, 1, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K9, 1, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K10, 1, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K11, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K12, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K13, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K14, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K15, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K16, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K17, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K18, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K19, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K21, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K22, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K23, NONE, DEEP),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -1,43 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC1220 */
|
||||
0x10ec1220, /* Vendor ID */
|
||||
0x155850d3, /* Subsystem ID */
|
||||
12, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x155850d3),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x0421101f),
|
||||
AZALIA_PIN_CFG(0, 0x15, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x04a11040),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x04451150),
|
||||
/* Intel, KabylakeHDMI */
|
||||
0x8086280b, /* Vendor ID */
|
||||
0x80860101, /* Subsystem ID */
|
||||
4, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(2, 0x80860101),
|
||||
AZALIA_PIN_CFG(2, 0x05, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x06, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x07, 0x18560010),
|
||||
/* Nvidia, GPU93HDMI/DP */
|
||||
0x10de0093, /* Vendor ID */
|
||||
0x155850d3, /* Subsystem ID */
|
||||
5, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x155850d3),
|
||||
AZALIA_PIN_CFG(0, 0x04, 0x185600f0),
|
||||
AZALIA_PIN_CFG(0, 0x05, 0x185600f0),
|
||||
AZALIA_PIN_CFG(0, 0x06, 0x185600f0),
|
||||
AZALIA_PIN_CFG(0, 0x07, 0x585600f0),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
@ -1,245 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#ifndef __ACPI__
|
||||
|
||||
/* Pad configuration in ramstage. */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD2, NATIVE, PWROK),
|
||||
PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD6, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_GPI(GPD7, UP_20K, PWROK),
|
||||
PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD9, UP_20K, PWROK),
|
||||
PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD11, UP_20K, PWROK),
|
||||
_PAD_CFG_STRUCT(GPP_A0, 0x44000401, 0x0000),
|
||||
PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A10, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_A11, UP_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_A12, 1, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_A15, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A16, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A17, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A18, UP_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_A19, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A20, UP_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_A21, 1, NONE, PLTRST),
|
||||
PAD_CFG_TERM_GPO(GPP_A22, 1, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_A23, 1, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_B0, 0x42080100, 0x3000),
|
||||
PAD_CFG_GPI(GPP_B1, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_B2, UP_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_B3, 1, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_B4, 1, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_B6, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_B7, 1, NONE, PLTRST),
|
||||
PAD_CFG_TERM_GPO(GPP_B8, 1, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_B9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B11, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_B12, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_B15, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_B16, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_B17, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_B18, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_B19, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_B20, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_B21, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_B22, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_C2, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_C3, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_C4, UP_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_C5, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C6, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_C7, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_C8, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_C9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C10, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_C11, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_C12, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_C13, UP_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_C14, 1, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_C15, 1, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_C18, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_C19, NONE, PLTRST, NF1),
|
||||
PAD_CFG_GPI(GPP_C20, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_C21, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_C22, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_C23, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D0, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D1, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D2, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D3, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_D4, NONE, PLTRST, NF2),
|
||||
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3),
|
||||
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3),
|
||||
PAD_CFG_GPI(GPP_D7, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D8, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D9, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D10, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D11, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D12, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D13, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D14, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D15, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D16, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_D17, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D18, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D19, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D20, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_D21, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D22, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_D23, NONE, PLTRST, NF2),
|
||||
PAD_CFG_GPI(GPP_E0, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E2, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_E3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E4, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E6, UP_20K, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_E7, 0x80800100, 0x0000),
|
||||
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E9, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_E10, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_E11, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_E12, UP_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_F0, 0, NONE, PLTRST),
|
||||
PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_F2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F3, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F4, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F5, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_F7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F8, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F10, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F11, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F12, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F13, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F14, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F15, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F16, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F17, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F18, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_F22, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_F23, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G0, DN_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_G1, DN_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_G2, DN_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_G3, DN_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_G4, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_G5, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_G6, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_G7, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1),
|
||||
_PAD_CFG_STRUCT(GPP_H4, 0x40880100, 0x3000),
|
||||
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_H7, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H8, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H9, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H10, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H11, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H14, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H15, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_H16, 0, NONE, PLTRST),
|
||||
PAD_CFG_TERM_GPO(GPP_H17, 0, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_H18, UP_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_H19, 1, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_H20, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H21, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H22, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H23, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I0, UP_20K, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_I1, 0x46880100, 0x0000),
|
||||
_PAD_CFG_STRUCT(GPP_I2, 0x46880100, 0x0000),
|
||||
_PAD_CFG_STRUCT(GPP_I3, 0x46880100, 0x0000),
|
||||
PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_I5, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_I6, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_I7, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_I8, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_I9, UP_20K, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_I10, 0x82880100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_I11, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_I12, DN_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_I13, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_I14, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J1, NONE, DEEP, NF2),
|
||||
PAD_CFG_GPI(GPP_J2, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_J3, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_J8, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_J9, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_J10, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_J11, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K0, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K1, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K2, UP_20K, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_K3, 0x80880100, 0x3000),
|
||||
PAD_CFG_GPI(GPP_K4, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K5, UP_20K, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_K7, UP_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K8, 1, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K9, 1, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K10, 1, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K11, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K12, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K13, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K14, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K15, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K16, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K17, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K18, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K19, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_K20, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K21, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K22, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K23, NONE, DEEP),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -1,42 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC1220 */
|
||||
0x10ec1220, /* Vendor ID */
|
||||
0x155865e5, /* Subsystem ID */
|
||||
12, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x155865e5),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x0421101f),
|
||||
AZALIA_PIN_CFG(0, 0x15, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x04a11040),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x04451150),
|
||||
/* Intel, KabylakeHDMI */
|
||||
0x8086280b, /* Vendor ID */
|
||||
0x80860101, /* Subsystem ID */
|
||||
4, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(2, 0x80860101),
|
||||
AZALIA_PIN_CFG(2, 0x05, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x06, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x07, 0x18560010),
|
||||
/* Nvidia, GPU9eHDMI/DP */
|
||||
0x10de009e, /* Vendor ID */
|
||||
0x155865e5, /* Subsystem ID */
|
||||
4, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x155865e5),
|
||||
AZALIA_PIN_CFG(0, 0x04, 0x185600f0),
|
||||
AZALIA_PIN_CFG(0, 0x06, 0x185600f0),
|
||||
AZALIA_PIN_CFG(0, 0x07, 0x185600f0),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
@ -1,297 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#define DGPU_RST_N GPP_F8
|
||||
#define DGPU_PWR_EN GPP_F9
|
||||
#define DGPU_GC6 GPP_K11
|
||||
|
||||
#ifndef __ACPI__
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
|
||||
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
|
||||
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
|
||||
PAD_CFG_GPO(DGPU_RST_N, 0, DEEP), // DGPU_RST#_PCH
|
||||
PAD_CFG_GPO(DGPU_PWR_EN, 0, DEEP), // DGPU_PWR_EN
|
||||
};
|
||||
|
||||
static const struct pad_config gpio_table[] = {
|
||||
/* ------- GPIO Group GPD ------- */
|
||||
PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),
|
||||
PAD_CFG_GPI(GPD2, NATIVE, PWROK),
|
||||
PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPI(GPD7, NONE, PWROK),
|
||||
PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPO(GPD9, 0, PWROK),
|
||||
PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPI(GPD11, NONE, PWROK),
|
||||
_PAD_CFG_STRUCT(GPD12, 0x04000300, 0x0000),
|
||||
|
||||
/* ------- GPIO Group GPP_A ------- */
|
||||
PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_A7, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A8, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A9, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A10, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A11, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A12, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A13, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A14, NONE, DEEP),
|
||||
|
||||
/* ------- GPIO Group GPP_B ------- */
|
||||
_PAD_CFG_STRUCT(GPP_B0, 0x40100100, 0x3000),
|
||||
PAD_CFG_GPI(GPP_B1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B2, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_B3, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_B4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B6, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_B8, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B11, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_B15, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_B16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B17, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B18, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B21, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B22, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B23, NONE, DEEP),
|
||||
|
||||
/* ------- GPIO Group GPP_C ------- */
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_C2, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF3),
|
||||
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF3),
|
||||
PAD_CFG_GPI(GPP_C5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C8, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C14, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C15, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_C20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C21, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_C22, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_C23, NONE, DEEP),
|
||||
|
||||
/* ------- GPIO Group GPP_D ------- */
|
||||
PAD_CFG_GPI(GPP_D0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D3, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3),
|
||||
PAD_CFG_GPI(GPP_D7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D8, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_D9, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_D11, NATIVE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D14, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_D16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D17, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D18, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D21, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D22, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_D23, 1, DEEP),
|
||||
|
||||
/* ------- GPIO Group GPP_E ------- */
|
||||
PAD_CFG_GPI(GPP_E0, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E4, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E5, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPI(GPP_E6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E7, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E12, NONE, DEEP),
|
||||
|
||||
/* ------- GPIO Group GPP_F ------- */
|
||||
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF2),
|
||||
PAD_CFG_GPO(GPP_F1, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_F2, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_F3, 0, PLTRST),
|
||||
PAD_CFG_GPO(GPP_F4, 1, DEEP),
|
||||
PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_F6, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_F7, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F8, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_F9, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_F10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F14, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F15, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F16, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_F17, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_F18, 1, DEEP),
|
||||
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_F22, NONE),
|
||||
PAD_CFG_GPO(GPP_F23, 1, PLTRST),
|
||||
|
||||
/* ------- GPIO Group GPP_G ------- */
|
||||
PAD_CFG_GPI(GPP_G0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G2, DN_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_G3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G5, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_G6, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_G7, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_G8, NATIVE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G10, NATIVE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G11, NONE, DEEP),
|
||||
PAD_NC(GPP_G12, NATIVE),
|
||||
PAD_NC(GPP_G13, NATIVE),
|
||||
PAD_CFG_GPI(GPP_G14, NATIVE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G15, NONE, DEEP),
|
||||
|
||||
/* ------- GPIO Group GPP_H ------- */
|
||||
PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_H5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H8, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H14, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H15, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_H16, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_H17, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_H18, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H19, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H20, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H21, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H22, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_H23, 1, DEEP),
|
||||
|
||||
/* ------- GPIO Group GPP_I ------- */
|
||||
PAD_CFG_NF(GPP_I0, NONE, PWROK, NF1),
|
||||
_PAD_CFG_STRUCT(GPP_I1, 0x46880100, 0x0000),
|
||||
_PAD_CFG_STRUCT(GPP_I2, 0x46880100, 0x0000),
|
||||
_PAD_CFG_STRUCT(GPP_I3, 0x46880100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_I4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I8, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_I9, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_I10, DN_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_I11, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_I12, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_I13, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_I14, NONE, PLTRST),
|
||||
|
||||
/* ------- GPIO Group GPP_J ------- */
|
||||
PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J1, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_J8, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_J9, NONE, DEEP),
|
||||
|
||||
/* ------- GPIO Group GPP_K ------- */
|
||||
PAD_CFG_GPO(GPP_K0, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_K1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K5, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_K6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_K7, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_K8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_K9, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_K10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K11, NONE, PLTRST),
|
||||
|
||||
/* ------- GPIO Group GPP_R ------- */
|
||||
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R5, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_R6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R8, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R11, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_R12, 0x40100100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_R13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R14, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R15, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R17, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R18, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R19, NONE, DEEP),
|
||||
|
||||
/* ------- GPIO Group GPP_S ------- */
|
||||
PAD_CFG_GPI(GPP_S0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_S1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_S2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_S3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_S4, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_S5, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_S6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_S7, NONE, DEEP),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -1,48 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC1220 */
|
||||
0x10ec1220, /* Vendor ID */
|
||||
0x155867f1, /* Subsystem ID */
|
||||
12, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x155867f1),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x0421101f),
|
||||
AZALIA_PIN_CFG(0, 0x15, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x04a11040),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x04451150),
|
||||
/* Intel, TigerlakeHDMI */
|
||||
0x80862812, /* Vendor ID */
|
||||
0x80860101, /* Subsystem ID */
|
||||
10, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(2, 0x80860101),
|
||||
AZALIA_PIN_CFG(2, 0x04, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x06, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x08, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0a, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0b, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0c, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0d, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0e, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0f, 0x18560010),
|
||||
/* Nvidia, GPU9eHDMI/DP */
|
||||
0x10de009e, /* Vendor ID */
|
||||
0x10de0000, /* Subsystem ID */
|
||||
4, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x10de0000),
|
||||
AZALIA_PIN_CFG(0, 0x04, 0x185600f0),
|
||||
AZALIA_PIN_CFG(0, 0x06, 0x185600f0),
|
||||
AZALIA_PIN_CFG(0, 0x07, 0x185600f0),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
@ -1,211 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#ifndef __ACPI__
|
||||
|
||||
/* Pad configuration in ramstage. */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),
|
||||
PAD_CFG_GPO(GPD2, 0, DEEP),
|
||||
PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPO(GPD7, 0, DEEP),
|
||||
PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPO(GPD9, 0, PWROK),
|
||||
PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD11, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1),
|
||||
_PAD_CFG_STRUCT(GPP_A6, 0x80100100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_A7, NONE, PLTRST),
|
||||
PAD_CFG_GPO(GPP_A8, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_A11, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_A13, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_A14, 0, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_A15, 0x46880100, 0x0000),
|
||||
PAD_CFG_GPO(GPP_A16, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_A17, 0, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_A18, 0x46880100, 0x0000),
|
||||
PAD_CFG_GPO(GPP_A19, 0, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_A20, 0x46880100, 0x0000),
|
||||
PAD_CFG_GPO(GPP_A21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A22, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_A23, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_B2, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_B3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B4, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
|
||||
PAD_CFG_GPO(GPP_B9, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B10, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_B15, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B16, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B17, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B18, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B19, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B20, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B22, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B23, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_C2, 1, PLTRST),
|
||||
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_C5, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_C8, NONE),
|
||||
PAD_NC(GPP_C9, NONE),
|
||||
PAD_NC(GPP_C10, NONE),
|
||||
PAD_NC(GPP_C11, NONE),
|
||||
PAD_NC(GPP_C12, NONE),
|
||||
PAD_NC(GPP_C13, NONE),
|
||||
PAD_NC(GPP_C14, NONE),
|
||||
PAD_NC(GPP_C15, NONE),
|
||||
PAD_NC(GPP_C16, NONE),
|
||||
PAD_NC(GPP_C17, NONE),
|
||||
PAD_NC(GPP_C18, NONE),
|
||||
PAD_NC(GPP_C19, NONE),
|
||||
PAD_NC(GPP_C20, NONE),
|
||||
PAD_NC(GPP_C21, NONE),
|
||||
PAD_NC(GPP_C22, NONE),
|
||||
PAD_NC(GPP_C23, NONE),
|
||||
PAD_CFG_GPO(GPP_D0, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_D1, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_D2, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D3, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D4, 1, PLTRST),
|
||||
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_D6, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_D9, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D10, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D11, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_D12, NATIVE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D13, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_D14, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_D15, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D16, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D17, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D18, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D19, 1, PLTRST),
|
||||
PAD_CFG_GPI(GPP_E0, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000),
|
||||
PAD_CFG_GPI(GPP_E2, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_E3, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_E4, 0, PLTRST),
|
||||
PAD_CFG_GPO(GPP_E5, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_E6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E8, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_E9, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_E10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E11, NONE, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_E12, 0x80100100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_E13, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_E15, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E16, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_E17, NONE, DEEP),
|
||||
PAD_NC(GPP_E18, NATIVE),
|
||||
PAD_NC(GPP_E19, NATIVE),
|
||||
PAD_CFG_GPO(GPP_E20, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E22, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E23, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_F7, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F8, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F9, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F10, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F11, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F12, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F13, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F14, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_F15, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F16, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F17, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_F18, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_F20, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_F21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F22, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F23, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H0, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H1, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_H2, 1, PLTRST),
|
||||
PAD_CFG_GPI(GPP_H3, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_H8, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H9, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_H10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H11, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_H12, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H13, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H14, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H15, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H16, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H17, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_H20, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H22, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_R5, 1, DEEP),
|
||||
PAD_CFG_GPI(GPP_R6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_R7, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_S0, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S1, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S2, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S3, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S4, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S5, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S6, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S7, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_T2, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_T3, 0, DEEP),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -1,48 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC1220 */
|
||||
0x10ec1220, /* Vendor ID */
|
||||
0x155867f5, /* Subsystem ID */
|
||||
12, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x155867f5),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x0421101f),
|
||||
AZALIA_PIN_CFG(0, 0x15, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x04a11040),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x04451150),
|
||||
/* Intel, Alderlake-PHDMI */
|
||||
0x8086281c, /* Vendor ID */
|
||||
0x80860101, /* Subsystem ID */
|
||||
10, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(2, 0x80860101),
|
||||
AZALIA_PIN_CFG(2, 0x04, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x06, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x08, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0a, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0b, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0c, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0d, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0e, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0f, 0x18560010),
|
||||
/* Nvidia, GPU9dHDMI/DP */
|
||||
0x10de009d, /* Vendor ID */
|
||||
0x10de0000, /* Subsystem ID */
|
||||
4, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x10de0000),
|
||||
AZALIA_PIN_CFG(0, 0x04, 0x185600f0),
|
||||
AZALIA_PIN_CFG(0, 0x06, 0x185600f0),
|
||||
AZALIA_PIN_CFG(0, 0x07, 0x185600f0),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
@ -1,272 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#ifndef __ACPI__
|
||||
|
||||
/* Pad configuration in ramstage. */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),
|
||||
PAD_CFG_GPO(GPD2, 0, DEEP),
|
||||
PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPD7, 0, DEEP),
|
||||
PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPO(GPD9, 0, PWROK),
|
||||
PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPD11, 0, DEEP),
|
||||
PAD_CFG_GPO(GPD12, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_A7, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A8, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A9, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_A10, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_A11, UP_20K, DEEP),
|
||||
PAD_CFG_GPO(GPP_A12, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A13, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_A14, 0, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_B0, 0x40100100, 0x3000),
|
||||
PAD_CFG_GPI(GPP_B1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B2, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_B3, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_B4, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B5, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B6, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B7, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B8, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B9, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B10, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B11, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B12, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_B15, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B16, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_B17, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_B18, NONE, PWROK, NF1),
|
||||
PAD_CFG_GPO(GPP_B19, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_B20, 0, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_B21, 0x42880100, 0x0000),
|
||||
PAD_CFG_GPO(GPP_B22, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_B23, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_C2, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF3),
|
||||
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF3),
|
||||
PAD_CFG_GPO(GPP_C5, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_C6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C8, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_C9, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_C10, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_C11, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_C12, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_C13, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_C14, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_C15, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_C20, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_C21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_C22, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_C23, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D0, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D1, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D2, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D3, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D4, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D5, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D6, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_D7, 0, DEEP),
|
||||
PAD_NC(GPP_D8, NONE),
|
||||
PAD_CFG_NF(GPP_D9, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D10, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D14, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D15, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D16, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D17, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D18, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D19, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_E0, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E1, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_E2, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E3, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_E4, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E5, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E6, 0, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_E7, 0x80100100, 0x0000),
|
||||
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E10, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E12, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_E13, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E14, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E15, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E16, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_E17, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_E18, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_E19, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E20, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_E21, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_F0, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_F1, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F2, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_F3, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F4, 0, DEEP),
|
||||
PAD_NC(GPP_F5, NONE),
|
||||
PAD_CFG_GPO(GPP_F6, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_F7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_F8, NONE, PLTRST),
|
||||
PAD_CFG_GPO(GPP_F9, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_F10, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_F11, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F12, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F13, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F14, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_F15, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_F16, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_F17, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_F18, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_F22, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_F23, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_G0, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_G1, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_G2, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_G3, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G4, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_G6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_G7, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_H0, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_H1, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_H2, NONE, DEEP),
|
||||
PAD_NC(GPP_H3, NONE),
|
||||
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_H10, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H11, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H12, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H13, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H14, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H15, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H16, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H17, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H18, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H19, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H20, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H22, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_H23, 0, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_I0, 0x86880100, 0x0000),
|
||||
PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1),
|
||||
_PAD_CFG_STRUCT(GPP_I2, 0x86880100, 0x0000),
|
||||
PAD_CFG_NF(GPP_I3, NONE, DEEP, NF1),
|
||||
_PAD_CFG_STRUCT(GPP_I4, 0x86880100, 0x0000),
|
||||
PAD_CFG_GPO(GPP_I5, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_I6, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_I7, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_I8, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_I9, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_I10, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_I11, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I14, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_I15, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_I16, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_I17, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_I18, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_I19, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_I20, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_I21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_I22, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J1, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_J8, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_J9, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_J10, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_J11, 0, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_K0, 0x42800100, 0x0000),
|
||||
PAD_CFG_GPO(GPP_K1, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_K2, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_K3, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPP_K4, 0, PWROK),
|
||||
PAD_CFG_GPO(GPP_K5, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_K6, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_K7, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_K8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_K9, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_K10, NONE, DEEP, NF2),
|
||||
PAD_CFG_GPO(GPP_K11, 0, DEEP),
|
||||
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_R5, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_R6, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_R7, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_R8, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_R9, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_R10, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_R11, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_R12, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_R13, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_R14, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_R15, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_R16, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_R17, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_R18, 0, DEEP),
|
||||
PAD_CFG_GPI(GPP_R19, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_R20, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_R21, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S0, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S1, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S2, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S3, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S4, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S5, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S6, 0, DEEP),
|
||||
PAD_CFG_GPO(GPP_S7, 0, DEEP),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -1,49 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC1220 */
|
||||
0x10ec1220, /* Vendor ID */
|
||||
0x1558d502, /* Subsystem ID */
|
||||
12, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x1558d502),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x0421101f),
|
||||
AZALIA_PIN_CFG(0, 0x15, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x04a11040),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x04451150),
|
||||
/* Intel, RaptorlakeHDMI */
|
||||
0x80862818, /* Vendor ID */
|
||||
0x80860101, /* Subsystem ID */
|
||||
10, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(2, 0x80860101),
|
||||
AZALIA_PIN_CFG(2, 0x04, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x06, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x08, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0a, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0b, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0c, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0d, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0e, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x0f, 0x18560010),
|
||||
/* Nvidia, GenericHDMI */
|
||||
0x10de00a6, /* Vendor ID */
|
||||
0x10de0000, /* Subsystem ID */
|
||||
5, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x10de0000),
|
||||
AZALIA_PIN_CFG(0, 0x04, 0x185600f0),
|
||||
AZALIA_PIN_CFG(0, 0x05, 0x585600f0),
|
||||
AZALIA_PIN_CFG(0, 0x06, 0x185600f0),
|
||||
AZALIA_PIN_CFG(0, 0x07, 0x185600f0),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
Reference in New Issue
Block a user