models: Remove generated C files
These files are generated while running proprietary firmware, but once
they are added to coreboot they are no longer needed. They also quickly
become stale as the files are always changed in coreboot.
find models/ -name gpio.h -exec rm {} \;
find models/ -name hda_verb.c -exec rm {} \;
Signed-off-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
Tim Crawford
committed by
Jeremy Soller
Jeremy Soller
parent
e4960f163e
commit
77581d11fc
@@ -1,211 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef MAINBOARD_GPIO_H
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#define MAINBOARD_GPIO_H
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#include <soc/gpe.h>
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#include <soc/gpio.h>
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#ifndef __ACPI__
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/* Pad configuration in ramstage. */
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static const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),
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PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),
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PAD_CFG_GPO(GPD2, 0, DEEP),
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PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
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PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
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PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
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PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
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PAD_CFG_GPO(GPD7, 0, DEEP),
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PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
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PAD_CFG_GPO(GPD9, 0, PWROK),
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PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
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PAD_CFG_NF(GPD11, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1),
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PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
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PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
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PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
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PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
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PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1),
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_PAD_CFG_STRUCT(GPP_A6, 0x80100100, 0x0000),
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PAD_CFG_GPI(GPP_A7, NONE, PLTRST),
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PAD_CFG_GPO(GPP_A8, 0, DEEP),
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PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
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PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
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PAD_CFG_GPO(GPP_A11, 0, DEEP),
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PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
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PAD_CFG_GPO(GPP_A13, 1, PLTRST),
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PAD_CFG_GPO(GPP_A14, 0, DEEP),
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_PAD_CFG_STRUCT(GPP_A15, 0x46880100, 0x0000),
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PAD_CFG_GPO(GPP_A16, 1, DEEP),
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PAD_CFG_GPO(GPP_A17, 0, DEEP),
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_PAD_CFG_STRUCT(GPP_A18, 0x46880100, 0x0000),
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PAD_CFG_GPO(GPP_A19, 0, DEEP),
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_PAD_CFG_STRUCT(GPP_A20, 0x46880100, 0x0000),
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PAD_CFG_GPO(GPP_A21, 0, DEEP),
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PAD_CFG_GPO(GPP_A22, 0, DEEP),
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PAD_CFG_GPI(GPP_A23, UP_20K, DEEP),
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PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
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PAD_CFG_GPO(GPP_B2, 0, DEEP),
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PAD_CFG_GPI(GPP_B3, NONE, DEEP),
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PAD_CFG_GPI(GPP_B4, NONE, DEEP),
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PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2),
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PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2),
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PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
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PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
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PAD_CFG_GPO(GPP_B9, 0, DEEP),
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PAD_CFG_GPO(GPP_B10, 0, DEEP),
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PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1),
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PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
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PAD_CFG_GPO(GPP_B15, 0, DEEP),
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PAD_CFG_GPO(GPP_B16, 0, DEEP),
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PAD_CFG_GPO(GPP_B17, 0, DEEP),
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PAD_CFG_GPO(GPP_B18, 0, DEEP),
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PAD_CFG_GPO(GPP_B19, 0, DEEP),
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PAD_CFG_GPO(GPP_B20, 0, DEEP),
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PAD_CFG_GPO(GPP_B21, 0, DEEP),
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PAD_CFG_GPO(GPP_B22, 0, DEEP),
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PAD_CFG_GPO(GPP_B23, 0, DEEP),
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PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
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PAD_CFG_GPO(GPP_C2, 1, PLTRST),
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PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
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PAD_CFG_GPO(GPP_C5, 0, DEEP),
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PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
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PAD_NC(GPP_C8, NONE),
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PAD_NC(GPP_C9, NONE),
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PAD_NC(GPP_C10, NONE),
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PAD_NC(GPP_C11, NONE),
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PAD_NC(GPP_C12, NONE),
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PAD_NC(GPP_C13, NONE),
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PAD_NC(GPP_C14, NONE),
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PAD_NC(GPP_C15, NONE),
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PAD_NC(GPP_C16, NONE),
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PAD_NC(GPP_C17, NONE),
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PAD_NC(GPP_C18, NONE),
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PAD_NC(GPP_C19, NONE),
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PAD_NC(GPP_C20, NONE),
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PAD_NC(GPP_C21, NONE),
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PAD_NC(GPP_C22, NONE),
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PAD_NC(GPP_C23, NONE),
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PAD_CFG_GPO(GPP_D0, 1, DEEP),
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PAD_CFG_GPI(GPP_D1, NONE, DEEP),
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PAD_CFG_GPO(GPP_D2, 0, DEEP),
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PAD_CFG_GPO(GPP_D3, 0, DEEP),
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PAD_CFG_GPO(GPP_D4, 1, PLTRST),
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PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
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PAD_CFG_GPO(GPP_D6, 0, DEEP),
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PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
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PAD_CFG_GPO(GPP_D9, 0, DEEP),
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PAD_CFG_GPO(GPP_D10, 0, DEEP),
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PAD_CFG_GPO(GPP_D11, 0, DEEP),
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PAD_CFG_GPI(GPP_D12, NATIVE, DEEP),
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PAD_CFG_GPI(GPP_D13, NONE, DEEP),
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PAD_CFG_GPO(GPP_D14, 1, PLTRST),
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PAD_CFG_GPO(GPP_D15, 0, DEEP),
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PAD_CFG_GPO(GPP_D16, 0, DEEP),
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PAD_CFG_GPO(GPP_D17, 0, DEEP),
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PAD_CFG_GPO(GPP_D18, 0, DEEP),
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PAD_CFG_GPO(GPP_D19, 1, PLTRST),
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PAD_CFG_GPI(GPP_E0, NONE, DEEP),
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_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000),
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PAD_CFG_GPI(GPP_E2, NONE, DEEP),
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PAD_CFG_GPO(GPP_E3, 1, PLTRST),
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PAD_CFG_GPO(GPP_E4, 0, PLTRST),
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PAD_CFG_GPO(GPP_E5, 0, DEEP),
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PAD_CFG_GPI(GPP_E6, NONE, DEEP),
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PAD_CFG_GPI(GPP_E7, NONE, DEEP),
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PAD_CFG_GPI(GPP_E8, NONE, DEEP),
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PAD_CFG_GPO(GPP_E9, 1, DEEP),
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PAD_CFG_GPI(GPP_E10, NONE, DEEP),
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PAD_CFG_GPI(GPP_E11, NONE, DEEP),
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_PAD_CFG_STRUCT(GPP_E12, 0x80100100, 0x0000),
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PAD_CFG_GPI(GPP_E13, NONE, DEEP),
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PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
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PAD_CFG_GPO(GPP_E15, 0, DEEP),
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PAD_CFG_GPO(GPP_E16, 0, DEEP),
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PAD_CFG_GPI(GPP_E17, NONE, DEEP),
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_PAD_CFG_STRUCT(GPP_E18, 0x44001300, 0x3c00),
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_PAD_CFG_STRUCT(GPP_E19, 0x44001300, 0x3c00),
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PAD_CFG_GPO(GPP_E20, 0, DEEP),
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PAD_CFG_GPO(GPP_E21, 0, DEEP),
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PAD_CFG_GPO(GPP_E22, 0, DEEP),
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PAD_CFG_GPO(GPP_E23, 0, DEEP),
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PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
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PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
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PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2),
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PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
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PAD_CFG_GPO(GPP_F7, 0, DEEP),
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PAD_CFG_GPO(GPP_F8, 0, DEEP),
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PAD_CFG_GPO(GPP_F9, 0, DEEP),
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PAD_CFG_GPO(GPP_F10, 0, DEEP),
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PAD_CFG_GPO(GPP_F11, 0, DEEP),
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PAD_CFG_GPO(GPP_F12, 0, DEEP),
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PAD_CFG_GPO(GPP_F13, 0, DEEP),
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PAD_CFG_GPO(GPP_F14, 0, DEEP),
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PAD_CFG_GPI(GPP_F15, NONE, DEEP),
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PAD_CFG_GPI(GPP_F16, NONE, DEEP),
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PAD_CFG_GPI(GPP_F17, NONE, DEEP),
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PAD_CFG_GPO(GPP_F18, 0, DEEP),
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PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
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PAD_CFG_GPO(GPP_F20, 1, PLTRST),
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PAD_CFG_GPO(GPP_F21, 0, DEEP),
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PAD_CFG_GPO(GPP_F22, 0, DEEP),
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PAD_CFG_GPO(GPP_F23, 0, DEEP),
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PAD_CFG_GPO(GPP_H0, 0, DEEP),
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PAD_CFG_GPO(GPP_H1, 1, PLTRST),
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PAD_CFG_GPO(GPP_H2, 1, PLTRST),
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PAD_CFG_GPI(GPP_H3, NONE, DEEP),
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PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
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PAD_CFG_GPO(GPP_H8, 0, DEEP),
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PAD_CFG_GPO(GPP_H9, 0, DEEP),
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PAD_CFG_GPI(GPP_H10, NONE, DEEP),
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PAD_CFG_GPI(GPP_H11, NONE, DEEP),
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PAD_CFG_GPO(GPP_H12, 0, DEEP),
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PAD_CFG_GPO(GPP_H13, 0, DEEP),
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PAD_CFG_GPO(GPP_H14, 0, DEEP),
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PAD_CFG_GPO(GPP_H15, 0, DEEP),
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PAD_CFG_GPO(GPP_H16, 0, DEEP),
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PAD_CFG_GPO(GPP_H17, 0, DEEP),
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PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
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PAD_CFG_GPO(GPP_H20, 0, DEEP),
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PAD_CFG_GPO(GPP_H21, 0, DEEP),
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PAD_CFG_GPO(GPP_H22, 0, DEEP),
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PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2),
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PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
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PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
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PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
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PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),
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PAD_CFG_GPO(GPP_R5, 1, DEEP),
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PAD_CFG_GPI(GPP_R6, NONE, DEEP),
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PAD_CFG_GPI(GPP_R7, NONE, DEEP),
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PAD_CFG_GPO(GPP_S0, 0, DEEP),
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PAD_CFG_GPO(GPP_S1, 0, DEEP),
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PAD_CFG_GPO(GPP_S2, 0, DEEP),
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PAD_CFG_GPO(GPP_S3, 0, DEEP),
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PAD_CFG_GPO(GPP_S4, 0, DEEP),
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PAD_CFG_GPO(GPP_S5, 0, DEEP),
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PAD_CFG_GPO(GPP_S6, 0, DEEP),
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PAD_CFG_GPO(GPP_S7, 0, DEEP),
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PAD_CFG_GPO(GPP_T2, 0, DEEP),
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PAD_CFG_GPO(GPP_T3, 0, DEEP),
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};
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#endif
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#endif
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@@ -1,48 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/azalia_device.h>
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const u32 cim_verb_data[] = {
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/* Realtek, ALC1220 */
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0x10ec1220, /* Vendor ID */
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0x155865f5, /* Subsystem ID */
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12, /* Number of entries */
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AZALIA_SUBVENDOR(0, 0x155865f5),
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AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
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AZALIA_PIN_CFG(0, 0x14, 0x0421101f),
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AZALIA_PIN_CFG(0, 0x15, 0x40000000),
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AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
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AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
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AZALIA_PIN_CFG(0, 0x18, 0x04a11040),
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AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
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AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
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AZALIA_PIN_CFG(0, 0x1b, 0x90170110),
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AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d),
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AZALIA_PIN_CFG(0, 0x1e, 0x04451150),
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/* Intel, Alderlake-PHDMI */
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0x8086281c, /* Vendor ID */
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0x80860101, /* Subsystem ID */
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10, /* Number of entries */
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AZALIA_SUBVENDOR(2, 0x80860101),
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AZALIA_PIN_CFG(2, 0x04, 0x18560010),
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AZALIA_PIN_CFG(2, 0x06, 0x18560010),
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AZALIA_PIN_CFG(2, 0x08, 0x18560010),
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AZALIA_PIN_CFG(2, 0x0a, 0x18560010),
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AZALIA_PIN_CFG(2, 0x0b, 0x18560010),
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AZALIA_PIN_CFG(2, 0x0c, 0x18560010),
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AZALIA_PIN_CFG(2, 0x0d, 0x18560010),
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AZALIA_PIN_CFG(2, 0x0e, 0x18560010),
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AZALIA_PIN_CFG(2, 0x0f, 0x18560010),
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/* Nvidia, GPU9dHDMI/DP */
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0x10de009d, /* Vendor ID */
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0x10de0000, /* Subsystem ID */
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4, /* Number of entries */
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AZALIA_SUBVENDOR(0, 0x10de0000),
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AZALIA_PIN_CFG(0, 0x04, 0x185600f0),
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AZALIA_PIN_CFG(0, 0x06, 0x185600f0),
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AZALIA_PIN_CFG(0, 0x07, 0x185600f0),
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};
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const u32 pc_beep_verbs[] = {};
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AZALIA_ARRAY_SIZES;
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Reference in New Issue
Block a user